3-103
PCI BUS INTERFACE
S5933
Targets selected with LOCK# deasserted during the
assertion of FRAME# (clock period 1 of Figure 15),
which encounter the assertion of LOCK# during the
following clock (clock period 2 of Figure 15) are
thereafter considered “locked.” A target, once locked,
requires that subsequent accesses to it deassert
LOCK# while FRAME# is asserted. Figure 16 show a
subsequent access to a locked target by the master
which locked it. Because LOCK# is owned by a
single master, only that master is able to deassert it
at the beginning of a transaction (allowing successful
access to the locked target). A locked target can only
be unlocked during the clock period following the last
data transfer of a transaction when the LOCK# signal
is deasserted.
An unlocked target ignores LOCK# when it observes
that LOCK# is already asserted during the first clock
period of a transaction. This allows other masters to
access other (unlocked) targets. If an access to a
locked target is attempted by a master other than the
one that locked it, the target responds with a retry
request, as shown in Figure 17.
The S5933 responds to and supports bus masters
which lock it as a target. When the S5933 is a bus
master, it never attempts to lock a target, but it hon-
ors a target’s request for retry if that target is locked
by another master.
Figure 16. Access to a Locked Target by its Owner
PCI CLOCK
FRAME #
LOCK #
AD [31:0]
IRDY#
TRDY#
DEVSEL#
ADDRESS
DATA
1
2
3
45
CONDITION
WHICH
UNLOCKS
TARGET
LOCKED
TARGET
IDENTIFIES
OWNER
DATA
(T)
(I)
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
Figure 17. Access Attempt to a Locked Target
PCI CLOCK
FRAME #
LOCK #
AD [31:0]
IRDY#
TRDY#
DEVSEL#
STOP#
ADDRESS
DATA
1
2
3
45
CAUSES TARGET
RETRY TERMINATION
LOCKED
TARGET IDENTIFIES
THAT BUS MASTER
IS NOT ITS OWNER
(T)
(I)
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET