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3-69
ADD-ON BUS OPERATION REGISTERS
S5933
ADD-ON CONTROLLED BUS MASTER
WRITE ADDRESS REGISTER (MWAR)
Register Name:
Master Write Address
Add-On Address Offset: 24h
Power-up value:
00000000h
Attribute:
Read/Write
Size:
32 bits
This register is only accessible when Add-On initiated
bus mastering is enabled.
This register is used to establish the PCI address for
data moving from the Add-On bus to the PCI bus
during PCI bus memory write operations. It consists
of a 30-bit counter with the low-order two bits
hardwired as zeros. Transfers may be any non-zero
byte length as defined by the transfer count register,
MWTC and must begin on a DWORD boundary. This
DWORD boundary starting constraint is placed upon
this controller’s PCI bus master transfers so that byte
lane alignment can be maintained between the
S5933 controller’s internal FIFO data path, the Add-
On interface, and the PCI bus.
Note: Applications which require a non-DWORD
starting boundary will need to move the first few
bytes under software program control (and without
using the FIFO) to establish a DWORD boundary.
After the DWORD boundary is established the S5933
can begin the task of PCI bus master data transfers.
The Master Write Address Register is continually up-
dated during the transfer process and will always be
pointing to the next unwritten location. Reading of
this register during a transfer process (done when the
S5933 controller is functioning as a target, i.e. not a
bus master) is permitted and may be used to monitor
the progress of the transfer. During the address
phase for bus master write transfers, the two least
significant bits presented on the PCI bus pins
AD[31:0] will always be zero. This identifies to the
target memory that the burst address sequence will
be in a linear order rather than in an Intel 486 or
Pentium cache line fill sequence. Also, the PCI bus
address bit A1 will always be zero when this control-
ler is the bus master. This signifies to the target that
the S5933 controller is burst capable and that the
target should not arbitrarily disconnect after the first
data phase of this operation.
31
0
1
0
2
Bit
Value
DWORD Address (RO)
Write Transfer Address (R/W)
Figure 1. Add-On Controlled Bus Master Write Address Register