3-52
PCI BUS OPERATION REGISTERS
S5933
OUTGOING MAILBOX REGISTERS (OMB)
Register Names:
Outgoing Mailboxes 1-4
PCI Address Offset: 00h, 04h, 08h, 0Ch
Power-up value:
XXXXXXXXh
Attribute:
Read/Write
Size:
32 bits
These four DWORD registers provide a method for
sending command or parameter data to the Add-On
system. PCI bus operations to these registers may
be in any width (byte, word, or DWORD). Writing to
these registers can be a source for Add-On bus inter-
rupts (if desired) by enabling their interrupt genera-
tion through the use of the Add-On’s interrupt control/
status register.
INCOMING MAILBOX REGISTERS (IMB)
Register Names:
Incoming Mailboxes 1-4
PCI Address Offset: 10h, 14h, 18h, 1Ch
Power-up value:
XXXXXXXXh
Attribute:
Read Only
Size:
32 bits
These four DWORD registers provide a method for
receiving user defined data from the Add-On system.
PCI bus read operations to these registers may be in
any width (byte, word, or DWORD). Only read opera-
tions are supported. Reading from these registers can
optionally cause an Add-On bus interrupt (if desired)
by enabling their interrupt generation through the use
of the Add-On’s interrupt control/status register.
Mailbox 4, byte 3 only exists as device pins on the
S5933 devices when used with a serial nonvolatile
memory.
This location provides access to the bidirectional
FIFO. Separate registers are used when reading
from or writing to the FIFO. Accordingly, it is not pos-
sible to read what was written to this location. The
FIFO registers are implicitly involved in all bus master
operations and, as such, should not be accessed
during active bus master transfers. When operating
upon the FIFOs with software program transfers in-
volving word or byte operations, the
endian sequence
of the FIFO should be established as described un-
der FIFO Endian Conversion Management in order to
preserve the internal FIFO data ordering and flag
management. The FIFO’s fullness may be observed
by reading the master control- status registeror
MCSR register.
FIFO REGISTER PORT (FIFO)
Register Name:
FIFO Port
PCI Address Offset: 20h
Power-up value:
XXXXXXXXh
Attribute:
Read/Write
Size:
32 bits