参数资料
型号: S5933QE
厂商: APPLIEDMICRO INC
元件分类: 总线控制器
英文描述: PCI BUS CONTROLLER, PQFP160
封装: PLASTIC, QFP-160
文件页数: 98/176页
文件大小: 823K
代理商: S5933QE
3-36
S5933
PCI CONFIGURATION REGISTERS
CACHE LINE SIZE REGISTER (CALN)
Register Name:
Cache Line Size
Address Offset:
0Ch
Power-up value:
00h, hardwired
Boot-load:
not used
Attribute:
Read Only
Size:
8 bits
This register is hardwired to 0. The cache line con-
figuration register is used by the system to define the
cache line size in doubleword (64-bit) increments.
This controller does not use the “Memory Write and
Invalidate” PCI bus cycle commands when operating
in the bus master mode, and therefore does not inter-
nally require this register. When operating in the tar-
get mode, this controller does not have the
connections necessary to “snoop” the PCI bus and
accordingly cannot employ this register in the detec-
tion of burst transfers that cross a line boundary.
Figure 7. Cache Line Size Register
7
0
00h
Cache Line Size (RO)
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