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参数资料
| 型号： | S5933QE |
| 厂商： | APPLIEDMICRO INC |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封装： | PLASTIC, QFP-160 |
| 文件页数： | 28/176页 |
| 文件大小： | 823K |
| 代理商： | S5933QE |
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3-136
FIFO OVERVIEW
S5933
The Bus Master Control/Status (MCSR) PCI Opera-
tion register allows a PCI host to monitor FIFO activ-
ity and control FIFO operation. Reset controls allow
the PCI to Add-On FIFO and Add-On to PCI FIFO
flags to be reset (individually). Status bits indicate if
the PCI to Add-On FIFO is empty, has four or more
open spaces, or is full. Status bits also indicate if the
Add-On to PCI FIFO is empty, has four or more full
locations or is full. Finally, FIFO PCI bus mastering is
monitored/controlled though this register.
The Add-On General Control/Status (AGCSTS) Add-
On Operation Register allows an Add-On CPU to
monitor FIFO activity and control FIFO operation. Re-
set controls allow the PCI to Add-On FIFO and Add-
On to PCI FIFO flags to be reset (individually). Status
bits indicate if the PCI to Add-On FIFO is empty, has
four or more open spaces, or is full. Status bits also
indicate if the Add-On to PCI is empty, has four or
more full spaces or is full. FIFO bus mastering status
may be monitored through this register, but all bus
master configuration is through the MCSR PCI Op-
eration Register.
PCI Initiated FIFO Bus Mastering Setup
For PCI initiated bus mastering, the PCI host sets up
the S5933 to perform bus master transfers. The fol-
lowing tasks must be completed to setup FIFO bus
mastering:
1) Define interrupt capabilities. The PCI to Add-On
and/or Add-On to PCI FIFO can generate a PCI
interrupt to the host when the transfer count
reaches zero.
INTCSR
Bit 15
Enable Interrupt on read
transfer count equal zero
INTCSR
Bit 14
Enable Interrupt on write
transfer count equal zero
2) Reset FIFO flags. This may not be necessary,
but if the state of the FIFO flags is not known,
they should be initialized.
MCSR
Bit 26
Reset Add-On to PCI FIFO
flags
MCSR
Bit 25
Reset PCI to Add-On FIFO
flags
3) Define FIFO management scheme. These bits
define what FIFO condition must exist for the PCI
bus request (REQ#) to be asserted by the
S5933.
MCSR
Bit 13
PCI to Add-On FIFO
management scheme
MCSR
Bit 9
Add-On to PCI FIFO
management scheme
4) Define PCI to Add-On and Add-On to PCI FIFO
priority. These bits determine which FIFO has pri-
ority if both meet the defined condition to request
the PCI bus. If these bits are the same, priority
alternates, with read accesses occurring first.
MCSR
Bit 12
Read vs. write priority
MCSR
Bit 8
Write vs. read priority
5) Define transfer source/destination address.
These registers are written with the first address
that is to be accessed by the S5933. These ad-
dress registers are updated after each access to
indicate the next address to be accessed. Trans-
fers must start on DWORD boundaries.
MWAR
All
Bus master write address
MRAR
All
Bus master read address
6) Define transfer byte counts. These registers are
written with the number of bytes to be trans-
ferred. The transfer count does not have to be a
multiple of four bytes. These registers are up-
dated after each transfer to reflect the number of
bytes remaining to be transferred.
MWTC
All
Write transfer byte count
MRTC
All
Read transfer byte count
7) Enable Bus Mastering. Once steps 1-6 are com-
pleted, the FIFO may operate as a PCI bus mas-
ter. Read and write bus master operation may be
independently enabled or disabled.
MCSR
Bit 14
Enable PCI to Add-On FIFO
bus mastering
MCSR
Bit 10
Enable Add-On to PCI FIFO
bus mastering
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相关代理商/技术参数 |
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| S5935 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935_07 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
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