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参数资料
| 型号： | S5933QE |
| 厂商： | APPLIEDMICRO INC |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封装： | PLASTIC, QFP-160 |
| 文件页数： | 142/176页 |
| 文件大小： | 823K |
| 代理商： | S5933QE |
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3-78
ADD-ON BUS OPERATION REGISTERS
S5933
Table 4. Add-On General Control/Status Register
Bit
Description
31:29
nvRAM/EPROM Access Control. This field provides a method for access to the optional, external
non-volatile memory. Write operations are achieved by a sequence of byte operations involving
these bits and the 8-bit field of bits 23 through 16. The sequence requires that the low-order
address, high-order address, and then a data byte be loaded in order. Bit 31 of this field acts as
an enable/clock and ready for the access to the external memory. D31 must be written to a 1
before an access can begin, and subsequent accesses must wait for bit D31 to become zero
(ready).
D31
D30
D29
W/R
0
X
W
Inactive
1
0
W
Load low address byte
1
0
1
W
Load high address byte
1
0
W
Begin write
1
W
Begin read
0
X
R
Ready
1
X
R
Busy
Cautionary note: The non-volatile memory interface is also available for access by the PCI bus
interface. Accesses by both the Add-On and PCI bus to the nv memory are not directly supported
by this component. Software must be designed to prevent the simultaneous access of nv memory
to prevent data corruption within the memory and provide for accurate data retrieval.
28
Transfer Count Enable. When set, transfer counts are used for Add-On initiated bus master
transfers. When clear, transfer counts are ignored.
27
Mailbox Flag Reset. Writing a 1 to this bit causes all mailbox status flags to become reset
(EMPTY). It is not necessary to write this bit as 0 because it is used internally to produce a reset
pulse. Since reading of this bit will always produce zeros, this bit is write only.
26
PCI to Add-On FIFO Status Reset. Writing a 1 to this bit causes the Inbound (Bus master reads)
FIFO empty flag to set indicating empty and the FIFO FULL flag to reset and the FIFO Four Plus
spaces flag to set. It is not necessary to write this bit as 0 because it is used internally to produce
a reset pulse. Since reading of this bit would always produce zeros, this bit is write only.
25
Add-On to PCI FIFO Status Reset. Writing a one to this bit causes the Outbound (Bus master
writes) FIFO empty flag to set indicating empty and the FIFO FULL flag to reset and the FIFO
Four Plus words available flag to reset. It is not necessary to write this bit as zero because it is
used internally to produce a reset pulse. Since reading of this bit would always produce zeros,
this bit is write only.
24
Reserved. Always zero.
23:16
Non-volatile memory address/data port. This 8-bit field is used in conjunction with bit 31, 30 and
29 of this register to access the external non-volatile memory. The contents written are either low
address, high address, or data as defined by bits 30 and 29. This register will contain the external
non-volatile memory data when the proper read sequence for bits 31 through 29 is performed.
15:12
BIST condition code. This field is directly connected to the PCI configuration self test register. Bit
15 through 12 maps with the BIST register bits 3 through 0, respectively.
11:8
Reserved. Always zero.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| S5935 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935_07 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
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