- 您现在的位置：买卖IC网 > PDF目录98071 > S5933QE (APPLIEDMICRO INC) PCI BUS CONTROLLER, PQFP160 PDF资料下载
参数资料
| 型号： | S5933QE |
| 厂商： | APPLIEDMICRO INC |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封装： | PLASTIC, QFP-160 |
| 文件页数： | 50/176页 |
| 文件大小： | 823K |
| 代理商： | S5933QE |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页当前第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页
3-156
PASS-THRU OVERVIEW
S5933
To write data into the APTD Register, the PTBEn#
output and the BEn# input must both be asserted.
The following describes how APTD Register writes
are controlled:
Write BYTE3 if PTBE3# AND BE3# are asserted
Write BYTE2 if PTBE2# AND BE2# are asserted
Write BYTE1 if PTBE1# AND BE1# are asserted
Write BYTE0 if PTBE0# AND BE0# are asserted
After each byte is written into the Pass-Thru data
register, its corresponding PTBE[3:0]# output is
deasserted. This allows Add-On logic to monitor
which bytes have been written, and which bytes re-
main to be written. When all bytes requested by the
PCI initiator have been written, the PTBE[3:0]# are all
be deasserted, and the Add-On asserts PTRDY#.
Figure 11 shows Pass-Thru operation for a region
defined for an 8-bit Add-On bus interface. As the 8-bit
device is connected only to DQ[7:0], the device must
access APTD one byte at a time.
The PCI initiator has performed a 32-bit write of
08D49A30h to Pass-Thru region zero. PTBE[3:0]#
are all asserted. At clock 1, the Add-On begins read-
ing the APTD Register (asserting SELECT#,
ADR[6:2], and RD#). Add-On logic asserts BE0#, and
BYTE0 of APTD is driven on DQ[7:0]. At the rising
edge of clock 2, BE0# is sampled by the S5933 and
PTBE0# is deasserted. PTBE[3:1]# are still asserted.
During clock 2, only BE1# is activated, and BYTE1 of
APTD is driven on DQ[7:0]. At the rising edge of
clock 3, BE1# is sampled by the S5933 and PTBE1#
is deasserted. PTBE[3:2]# are still asserted.
This process continues until all bytes have been read
from the APTD Register. During clock 5, RD# is
deasserted and PTRDY# is asserted. PTRDY# is
sampled by the S5933 at the rising edge of clock 6,
and the current data phase is completed. PTATN# is
deasserted and new data can be written from the PCI
bus. In this example, the byte enables are asserted,
sequentially, from BE0# to BE3#. This is not re-
quired, bytes may be accessed in any order.
New data is written by the PCI initiator and is avail-
able in the APTD Register during clock 7. RD# is
asserted and the byte enables are cycled again. With
each new data from the PCI bus, the Add-On se-
quences through the byte enables to access APTD
via DQ[7:0].
For 16-bit peripheral devices, the byte steering works
in the same way. Because the Add-On data bus is
16-bits wide, only two 16-bit cycles are required to
access the entire APTD Register. Two byte enables
can be asserted during each access.
In Figure 11, RD# is held low and the byte enables
are changed each clock. This assumes the Add-On
can accept data at one byte per clock. This is the
fastest transfer possible. For slower devices, wait
states may be added.
As long as the byte enables remain in a given state,
the corresponding byte of the APTD Register is con-
nected to the DQ bus (the RD# or WR# pulse may
also be lengthened). Each access may be extended
for slower Add-On devices, but extending individual
data phases for Pass-Thru cycles may result in the
S5933 requesting retries by the initiator.
10
11
12
13
9
8
7
6
5
4
3
2
3Ch
2Ch
Fh
0h
1h
3h
7h
Fh
0h
1h
3h
7h
Fh
1
BPCLK
PTATN#
PTWR
PTBE[3:0]#
PTNUM[1:0]
PTBURST#
Fh
Bh
Eh
Dh
7h
Fh
Eh
Dh
Bh
7h
Fh
D4h
30h
9Ah
08h
DDh
CCh
BBh
AAh
ADDR
0
SELECT#
BE[3:0]#
PTADR#
PTRDY#
ADR[6:2]
RD#
DQ[7:0]
Figure 11. Pass-Thru Write to an 8-bit Add-On Device
Note: 8 Bit Mode BE’s are E, D, B, 7; 16 Bit Mode BE’s are C, 3.
相关PDF资料 |
PDF描述 |
|---|---|
| S6A0032 | 16 X 80 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC138 |
| S6A0069 | 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC80 |
| S6A0078 | 34 X 120 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC183 |
| S80296SA40 | 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 |
| S80486-DX4-75-S-V-8-B | 32-BIT, 75 MHz, MICROPROCESSOR, PQFP208 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S5935 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935_07 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
发布紧急采购，3分钟左右您将得到回复。