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参数资料
| 型号： | S5933QE |
| 厂商： | APPLIEDMICRO INC |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封装： | PLASTIC, QFP-160 |
| 文件页数： | 29/176页 |
| 文件大小： | 823K |
| 代理商： | S5933QE |
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3-137
FIFO OVERVIEW
S5933
The order of the tasks listed above is not particularly
important. It is recommended that bus mastering be
enabled as the last step. Some applications may
choose to leave bus mastering enabled and start
transfers by writing a non-zero value to the transfer
count registers. This also works, provided the entire
transfer count is written in a single access. As a num-
ber of the configuration bits and the two enable bits
are all in the MCSR register, it may be most efficient
for the FIFO configuration bits to be set with the
same register access that enables bus mastering.
If interrupts are enabled, a host interrupt service rou-
tine is also required. The service routine determines
the source of the interrupt and resets the interrupt. As
mailbox registers may also be configured to generate
interrupts, the exact source of the interrupt is indi-
cated in the PCI Interrupt Control/Status Register
(INTCSR). Typically, the interrupt service routine is
used to setup the next transfer by writing new ad-
dresses and transfer counts, but some applications
may also require other actions. If read transfer or
write transfer complete interrupts are enabled, mas-
ter and target abort interrupts are automatically en-
abled. These indicate a transfer error has occurred.
Writing a one to these bits clears the corresponding
interrupt.
INTCSR
Bit 21
Target abort caused interrupt
INTCSR
Bit 20
Master abort caused interrupt
INTCSR
Bit 19
Read transfer complete
caused interrupt
INTCSR
Bit 18
Write transfer complete
caused interrupt
Add-On Initiated FIFO Bus Mastering Setup
For Add-On initiated bus mastering, the Add-On sets
up the S5933 to perform bus master transfers. The
following tasks must be completed to setup FIFO bus
mastering:
1) Define transfer count abilities. For Add-On initi-
ated bus mastering, transfer counts may be ei-
ther enabled or disabled. Transfer counts for
read and write operations cannot be individually
enabled.
AGCSTS
Bit 28
Enable transfer count for
read and write bus master
transfers
2) Define interrupt capabilities. The PCI to Add-On
and/or Add-On to PCI FIFO can generate an in-
terrupt to the Add-On when the transfer count
reaches zero (if transfer counts are enabled).
AINT
Bit 15
Enable interrupt on read
transfer count equal zero
AINT
Bit 14
Enable interrupt on write
transfer count equal zero
3) Reset FIFO flags. This may not be necessary,
but if the state of the FIFO flags is not known,
they should be initialized.
AGCSTS
Bit 25
Reset Add-On to PCI FIFO
flags
AGCSTS
Bit 26
Reset PCI to Add-On FIFO
flags
4) Define FIFO management scheme. These bits
define what FIFO condition must exist for the PCI
bus request (REQ#) to be asserted by the
S5933. This must be programmed through the
PCI interface.
MCSR
Bit 13
PCI to Add-On FIFO
management scheme
MCSR
Bit 9
Add-On to PCI FIFO
management scheme
5) Define PCI to Add-On and Add-On to PCI FIFO
priority. These bits determine which FIFO has pri-
ority if both meet the defined condition to request
the PCI bus. If these bits are the same, priority
alternates, with read accesses occurring first.
This must be programmed through the PCI inter-
face.
MCSR
Bit 12
Read vs. write priority
MCSR
Bit 8
Write vs. read priority
6) Define transfer source/destination address.
These registers are written with the first address
that is to be accessed by the S5933. These ad-
dress registers are updated after each access to
indicate the next address to be accessed. Trans-
fers must start on DWORD boundaries.
MWAR
All
Bus master write address
MRAR
All
Bus master read address
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相关代理商/技术参数 |
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| S5935 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935_07 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
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