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参数资料
| 型号： | S5933QE |
| 厂商： | APPLIEDMICRO INC |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封装： | PLASTIC, QFP-160 |
| 文件页数： | 129/176页 |
| 文件大小： | 823K |
| 代理商： | S5933QE |
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3-65
PCI BUS OPERATION REGISTERS
S5933
Table 4. Bus Master Control/Status Register (Continued)
Bit
Description
15
Enable memory read multiple during S5933 bus mastering mode.
14
Read Transfer Enable. This bit must be set to a one for S5933 PCI bus master read transfers to
take place. Writing a zero to this location will suspend an active transfer. An active transfer is one
in which the transfer count is not zero.
13
Read FIFO management scheme. When set to a 1, this bit causes the controller to refrain from
requesting the PCI bus unless it has four or more vacant FIFO locations to fill. Once the controller
is granted the PCI bus or is in possession of the bus due to the write channel, this constraint is
not meaningful. When this bit is zero the controller will request the PCI bus if it has at least one
vacant FIFO word.
12
Read versus Write priority. This bit controls the priority of read transfers over write transfers.
When set to a 1 with bit D8 as zero this indicates that read transfers always have priority over
write transfers; when set to a one with D8 as one, this indicates that transfer priorities will
alternate equally between read and writes.
11
Reserved. Always zero.
10
Write Transfer Enable. This bit must be set to a one for PCI bus master write transfers to take
place. Writing a zero to this location will suspend an active transfer. An active transfer is one in
which the transfer count is not zero.
9
Write FIFO management scheme. When set to a one this bit causes the controller to refrain from
requesting the PCI bus unless it has four or more FIFO locations filled. Once the S5933 controller
is granted the PCI bus or is in possession of the bus due to the write channel, this constraint is
not meaningful. When this bit is zero the controller will request the PCI bus if it has at least one
valid FIFO word.
8
Write versus Read priority. This bit controls the priority of write transfers over read transfers.
When set to a one with bit D12 as zero this indicates that write transfers always have priority over
read transfers; when set to a one with D12 as one, this indicates that transfer priorities will
alternate equally between writes and reads.
7
Add-On to PCI Transfer Count Equal Zero (RO). This bit is a one to signify that the write transfer
count is all zeros.
6
PCI to Add-On Transfer Count Equals Zero (RO). This bit is a one to signify that the read transfer
count is all zeros.
5
Add-On to PCI FIFO Empty. This bit is a one when the Add-On to PCI bus FIFO is completely
empty.
4
Add-On to PCI 4+ words. This bit is a one when there are four or more FIFO words valid within
the Add-On to PCI bus FIFO.
3
Add-On to PCI FIFO Full. This bit is a one when the Add-On to PCI bus FIFO is completely full.
2
PCI to Add-On FIFO Empty. This bit is a one when the PCI bus to Add-On FIFO is completely
empty.
1
PCI to Add-On FIFO 4+ spaces. This bit signifies that there are at least four empty words within
the PCI to Add-On FIFO.
0
PCI to Add-On FIFO Full. This bit is a one when the PCI bus to Add-On FIFO is completely full.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| S5935 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935_07 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
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