- 您现在的位置：买卖IC网 > PDF目录98071 > S5933QE (APPLIEDMICRO INC) PCI BUS CONTROLLER, PQFP160 PDF资料下载
参数资料
| 型号： | S5933QE |
| 厂商： | APPLIEDMICRO INC |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封装： | PLASTIC, QFP-160 |
| 文件页数： | 176/176页 |
| 文件大小： | 823K |
| 代理商： | S5933QE |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页当前第176页
3-111
ADD-ON BUS INTERFACE
S5933
Accessing Non-Volatile Memory
The nv memory, if implemented, can be accessed
through the PCI interface or the Add-On interface.
Accesses from both the PCI side and the Add-On
side must be synchronous with the PCI clock
(BPCLK for the Add-On). Accesses to the nv memory
from the PCI interface are through the Bus Master
Control/Status Register (MCSR) PCI Operation Reg-
ister. Accesses to the nv memory from the Add-On
interface are through the Add-On General Control/Sta-
tus Register (AGCSTS) Add-On Operation Register.
Accesses to the MCSR register are from the PCI bus
and are, therefore, automatically synchronous to the
PCI clock. Accesses to the AGCSTS register from
the Add-On side must be synchronous with respect
to BPCLK.
Some nv memories may contain Expansion ROM
BIOS code for use by the host software. During ini-
tialization, the Expansion BIOS is located within sys-
tem memory. The starting location of the nv memory
is stored in the Expansion ROM Base Address Reg-
ister in the S5933 PCI Configuration Registers. A PCI
read from this region results in the S5933 performing
four consecutive byte access to the nv memory de-
vice. Writes to the nv memory are not allowed by
writing to this region. Writes to the nv memory must
be performed as described below.
The S5933 contains two latches within the MCSR
register to control and access the NVRAM. One is an
8 bit latch called the NVRAM Address/Data Register
which is used to hold NVRAM address and data in-
formation. The other is a 3 bit latch called the
NVRAM Access Control Register which is used to
direct the address and data information and to control
the NVRAM itself. Reading or writing to the NVRAM
is performed through bits D31:29 of this register.
These bits are enable and decode controls rather
than a command or instruction to be executed. D31
of this register is the primary enable bit which allows
all accesses to occur. When written to a ‘1’, D31
enables the decode bits D30 and D29 to direct the
data contained in the address/data latch, D23:16, to
the low address, high address or data latches. D31
should be thought of as “opening a door” where as
long as D31 = 1, then the door is open for address
or data information to be altered. The table on page
5-16 of the S5933 data book shows the D31:29 bit
combinations for reading, writing, and loading ad-
dress/data information. Additionally, D31 doubles as
an S5933 status bit. A ‘1’ indicates that the S5933 is
currently busy reading or writing to the NVRAM. A
‘0’ indicates a complete or inactive state.
For the examples below, we will assume the S5933
is I/O mapped with a base address of FC00h. These
examples will read one byte of the Vendor ID and
write one byte to the Vendor ID.
In
FC00h + 3Fh (offset of NVRAM Access Control Register) until D31 = 0 (not busy).
Out
FC00h + 3FH an 80h (CMD to load the low address byte). This sets decode bits and opens door for
low address latch.
Out
FC00h + 3Eh (offset of Address/Data Register) 40h (the low byte of the address desired) 40h goes
into latch but is not latched yet.
Out
FC00h + 3Fh an A0h (CMD to load the high address byte). This latches the low address through
changing the decode bits and opens the door for the high address latch.
Out
FC00h + 3Eh a 00h (the high byte of the address desired). 00h goes into the latch but is not latched
yet.
Out
FC00h + 3Fh an 00h (inactive CMD). This latches the high address through the disabling D31,
‘closes the door’.
Out
FC00h + 3Eh DATA (the data byte to be written). DATA byte goes into the latch but is not latched
yet.
Out
FC00h + 3Fh a C0h (CMD to write the data byte). This latches the data byte through changing the
decode bits and begins to write NVRAM data operation.
In
FC00h + 3Fh until D31 = 0 (not busy).
Out
FC00h + 3Fh an E0h (CMD to read the address latched).
In
FC00h + 3Fh until D31 = 0 (not busy).
In
FC00h + 3Eh the data.
This example will write 1 byte from NVRAM location 0040h and read it back:
相关PDF资料 |
PDF描述 |
|---|---|
| S6A0032 | 16 X 80 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC138 |
| S6A0069 | 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC80 |
| S6A0078 | 34 X 120 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC183 |
| S80296SA40 | 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 |
| S80486-DX4-75-S-V-8-B | 32-BIT, 75 MHz, MICROPROCESSOR, PQFP208 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S5935 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935_07 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
发布紧急采购，3分钟左右您将得到回复。