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FIFO OVERVIEW
S5933
The configurable FIFO advance condition may be
used to transfer data to and from Add-On interfaces
which are not 32-bits wide. For a 16-bit Add-On bus,
the Add-On to PCI FIFO advance condition can be
set to byte 2. This allows a 16-bit write to the lower 16-
bits of the FIFO register (bytes 0 and 1) and a second
write to the upper 16-bits of the FIFO register (bytes
2 and 3). The FIFO does not advance until the
second access. This allows the Add-On to operate
with 16-bit data, while the PCI bus maintains a 32-bit
data path.
Notes:
1. During operation, the INTCSR FIFO advance condition bits
(D29:26) should only be changed when the FIFO is empty and
is idle on both the Add-On and PCI interfaces.
Endian Conversion
Bits D31:30 and D25:24 of the INTCSR PCI Opera-
tion Register control endian conversion operations for
the FIFO (Figure 1). When endian conversion is per-
formed, it affects data passing in either direction
through the FIFO interface. Figures 2a and 2b show
16-bit and 32-bit endian conversion. It is important to
note that endian conversion is performed on data BE-
FORE it enters the FIFO. This affects the FIFO ad-
vance condition. Example: the FIFO is configured to
perform 32-bit endian conversion on data, and the
FIFO advance condition is set to byte 0. Byte 3 is
written into the FIFO (BE3# asserted). After the
endian conversion, byte 3 becomes byte 0, and the
FIFO advances. This behavior must be considered
when not performing full 32-bit accesses to the FIFO.
Notes:
1. During operation, the INTCSR FIFO endian conversion bits
(D25:24) and 64-bit access bits (D31:30) should only be
changed when the FIFO is empty and is idle on both the Add-
On and PCI interfaces.
Figure 2a. 16-bit Endian Conversion
DESTINATION
D 31-24
D 23-16
D 15-8
D 7-0
BYTE 3
BYTE 2
BYTE 1
BYTE 0
BYTE 3
BYTE 2
BYTE 1
BYTE 0
D 31-24
D 23-16
D 15-8
D 7-0
SOURCE
Figure 2b. 32-bit Endian Conversion
DESTINATION
D 31-24
D 23-16
D 15-8
D 7-0
BYTE 3
BYTE 2
BYTE 1
BYTE 0
BYTE 3
BYTE 2
BYTE 1
BYTE 0
D 31-24
D 23-16
D 15-8
D 7-0
SOURCE