- 您现在的位置：买卖IC网 > PDF目录98071 > S5933QE (APPLIEDMICRO INC) PCI BUS CONTROLLER, PQFP160 PDF资料下载
参数资料
| 型号： | S5933QE |
| 厂商： | APPLIEDMICRO INC |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封装： | PLASTIC, QFP-160 |
| 文件页数： | 37/176页 |
| 文件大小： | 823K |
| 代理商： | S5933QE |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页当前第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页
3-144
PASS-THRU OVERVIEW
S5933
The Add-On PTADR# input directly accesses the
Pass-Thru Address Register and drives the contents
onto the data bus (no BPCLK rising edge is re-
quired). The byte enables, address, and SELECT#
inputs are ignored when PTADR# is asserted. RD#
and WR# must not be asserted when PTADR# is
asserted.
Clock 0: The PCI bus cycle address is stored in the
S5933 Pass-Thru Address Register.
Clock 1: The PCI address is recognized as an
access to Pass-Thru region 1. PCI data is
stored in the S5933 Pass-Thru Data
Register. PTATN# is asserted to indicate a
Pass-Thru access is occurring.
Clock 2: Pass-Thru status signals indicate what
action is required by Add-On logic. Pass-
Thru status outputs are valid when
PTATN# is active and are sampled by the
Add-On at the rising edge of clock 2.
PTBURST#
Deasserted. The access has
a single data phase.
PTNUM[1:0] 01. Indicates the PCI access
is to Pass-Thru region 1.
PTWR
Asserted. The Pass-Thru
access is a write.
PTBE[3:0]#
0h. Indicate the Pass-Thru
access is 32-bits.
The PTADR# input is asserted to read the
Pass-Thru Address Register. The byte en-
able, address, and SELECT# inputs are
changed during this clock to select the Pass-
Thru Data Register during clock cycle 3.
Clock 3: SELECT#, byte enable, and the address
inputs remain valid to read the Pass-Thru
Data Register at offset 2Ch. RD# is
asserted to drive data register contents
onto the DQ bus.
Clock 4: If PTRDY# is asserted at the rising edge of
clock 4, PTATN# is immediately deasserted
and the Pass-Thru access is completed at
clock 5.
Clock 5: If Add-On logic requires more time to read
the Pass-Thru Data Register (slower
memory or peripherals), PTRDY# can be
delayed, extending the cycle. PTRDY#
asserted at the rising edge of clock 5 causes
PTATN# to be immediately deasserted.
Clock 6: PTATN# and PTBURST# deasserted at
the rising edge of clock 6 indicates the
Pass-Thru access is complete. The S5933
can accept new Pass-Thru accesses from
the PCI bus at clock 7.
Single Cycle Pass-Thru Reads
A single cycle Pass-Thru read operation occurs when
a PCI initiator reads a single value from a Pass-Thru
region. PCI single cycle transfers consists of an ad-
dress phase and a one data phase. During the ad-
dress phase of the PCI transfer, the S5933 stores the
PCI address into the Pass-Thru Address Register
(APTA). If the S5933 determines that the address is
within one of its defined Pass-Thru regions, it indi-
cates to the Add-On that a write to the Pass-Thru
Data Register (APTD) is required.
Figure 3 shows a single cycle Pass-Thru read access
(Add-On write) using PTADR#. The Add-On reads
data from a source on the Add-On and writes it to the
APTD register.
Clock 0: PCI address information is stored in the
S5933 Pass-Thru Address Register. The PCI
cycle is recognized as an access to Pass-
Thru region 1. PTATN# is asserted by the
S5933 to indicate a Pass-Thru access is
occurring.
Clock 1: Pass-Thru status signals indicate what
action is required by Add-On logic. Pass-
Thru status outputs are valid when
PTATN# is active and are sampled by the
Add-On at the rising edge of clock 1.
PTBURST#
Deasserted. The access has
a single data phase.
PTNUM[1:0] 01. Indicates the PCI access
was to Pass-Thru region 1.
PTWR
Deasserted. The Pass-Thru
access is a read.
PTBE[3:0]#
0h. Indicate the Pass-Thru
access is 32-bits.
The PTADR# input is asserted to read the
Pass-Thru Address Register. The byte en-
able, address, and SELECT# inputs are
changed during this clock to select the Pass-
Thru Data Register during clock cycle 3.
Clock 2: This clock is required to avoid contention
on the DQ bus. Time must be allowed after
PTADR# is deasserted for the DQ outputs
to float before Add-On logic attempts to
write to the Pass-Thru Data Register.
Clock 3: SELECT#, byte enables, and the address
inputs remain valid to write the Pass-Thru
Data Register at offset 2Ch. If WR# is
asserted at the rising edge of clock 3, data
on the DQ bus is latched into APTD.
If PTRDY# is asserted at the rising edge of
clock 3, PTATN# is immediately deasserted
and the Pass-Thru access is completed at
clock 4.
相关PDF资料 |
PDF描述 |
|---|---|
| S6A0032 | 16 X 80 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC138 |
| S6A0069 | 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC80 |
| S6A0078 | 34 X 120 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC183 |
| S80296SA40 | 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 |
| S80486-DX4-75-S-V-8-B | 32-BIT, 75 MHz, MICROPROCESSOR, PQFP208 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S5935 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935_07 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
发布紧急采购，3分钟左右您将得到回复。