- 您现在的位置：买卖IC网 > PDF目录98071 > S5933QE (APPLIEDMICRO INC) PCI BUS CONTROLLER, PQFP160 PDF资料下载
参数资料
| 型号： | S5933QE |
| 厂商： | APPLIEDMICRO INC |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封装： | PLASTIC, QFP-160 |
| 文件页数： | 148/176页 |
| 文件大小： | 823K |
| 代理商： | S5933QE |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页当前第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页
3-84
INITIALIZATION
S5933
LOADING FROM SERIAL NV MEMORIES
SNV tied high indicates that a serial nv memory (or
no external device) is present. When serial nv memo-
ries are used, data transfer is performed through a
two-wire, bidirectional data transfer protocol as de-
fined by commercial serial EEPROM/Flash offerings.
These devices have the advantages of low pin
counts, small package size, and economical price.
A serial nv memory is considered valid if the first
serial accesses contain the correct per-byte acknowl-
edgments (see Figure 3). If the serial per-byte ac-
knowledgment is not observed, the S5933
determines that no external serial nv memory is
present and the AMCC default Configuration Register
values are used.
Two pins are used to transfer data between the
S5933 PCI controller and the external serial memory:
a serial clock pin, SCL, and a serial data pin, SDA.
The serial clock pin is an output from the S5933, and
the serial data pin is bidirectional. The serial clock is
derived by dividing the PCI bus clock by 512. This
means that the frequency of the serial clock is ap-
proximately 65 kHz for a 33-MHz PCI bus clock.
Communications with the serial memory involve sev-
eral clock transitions. A start event signals the
beginning of a transaction and is immediately fol-
lowed by an address transfer. Each address/data
transfer consists of 8 bits of information followed by a
1-bit acknowledgment. When the exchange is com-
plete, a stop event is issued. Figure 1 shows the
unique relationship defining both a start and stop
event. Figure 2 shows the required timing for ad-
dress/data with respect to the serial clock.
Table 1. Valid External Boot Memory Contents
Address
0040h-41h
0050h
0051
0052h
0053h
Data
not FFFFh
C2h, C1h or C0h
FFh
E8h
10h
Notes
This is the location that the S5933 PCI
Controller will load a customized vendor ID.
(FFFFh is an illegal vendor ID.)
This is the least significant byte of the region which
initializes the base address register #0 of the S5933
configuration register (Section 3.11). A value of C1h
assigns the 16 DWORD locations of the PCI operation
registers into I/O space, a value of C0h defines
memory space, a value of C2h defines memory space
below 1 Mbyte.
Required.
For random accesses, the sequence involves one
clock to define the start of the sequence, eight clocks
to send the slave address and read/write command,
followed by a one-clock acknowledge, and so on.
Figure 3 shows the sequence for a random write ac-
cess requiring 29 serial clock transitions. At the clock
speed for the S5933, this corresponds to one byte of
data transferred approximately every 0.5 millisec-
onds. Read accesses may be either random or se-
quential. Random read access requires a dummy
write to load the word address and require 39 serial
clock transitions. Figure 4 shows the sequence for a
random byte read.
To initialize the S5933 controller’s PCI Configuration
Registers, the smallest serial device necessary is a
128 x 8 organization. Although the S5933 controller
only requires 64 bytes, these bytes must begin at a
64-byte address offset (0040h through 007Fh). This
offset constraint permits the configuration image to
be shared with a memory containing expansion BIOS
code and the necessary preamble to identify an ex-
pansion BIOS. The largest serial device which may
be used is 2 Kbytes.
相关PDF资料 |
PDF描述 |
|---|---|
| S6A0032 | 16 X 80 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC138 |
| S6A0069 | 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC80 |
| S6A0078 | 34 X 120 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC183 |
| S80296SA40 | 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 |
| S80486-DX4-75-S-V-8-B | 32-BIT, 75 MHz, MICROPROCESSOR, PQFP208 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S5935 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935_07 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
发布紧急采购，3分钟左右您将得到回复。