参数资料
型号: S5933QE
厂商: APPLIEDMICRO INC
元件分类: 总线控制器
英文描述: PCI BUS CONTROLLER, PQFP160
封装: PLASTIC, QFP-160
文件页数: 25/176页
文件大小: 823K
代理商: S5933QE
3-133
FIFO OVERVIEW
S5933
written (or an empty FIFO is read) by a PCI initiator,
the S5933 requests a retry. The faster the Add-On
interface can empty (or fill) the FIFO, the less often
retries occur. With the S5933 as a PCI initiator, a
similar situation occurs. Not emptying or filling the
FIFO quickly enough results in the S5933 giving up
control of the PCI bus. Higher PCI bus data transfer
rates are possible through the FIFO with a synchro-
nous interface.
Additional Status/Control Signals for Add-On
Initiated Bus Mastering
If a serial non-volatile memory is used to configure the
S5933, and the device is configured for Add-On initi-
ated bus mastering, two additional FIFO status signals
and four additional control signals are available to the
Add-On interface. The FRF and FWE outputs provide
additional FIFO status information. Inputs FRC#,
FWC#, AMREN, and AMWEN provide additional FIFO
control. Applications may use these signals to monitor/
control FIFO flags and PCI bus requests. These new
signals are some of the lines that were used for byte-
wide nvram interface, but now are reconfigured. The
reconfigured lines are as follows:
Outputs:
E_ADDR (15)
FRF
FIFO Read Full: Indicates that the PCI to Add-On
FIFO is full.
E_ADDR (14)
FWE
FIFO Write Empty: Indicates that the Add-On to PCI
FIFO is empty.
Inputs:
EQ (7)
AMWEN
Add-On bus Mastering Write ENable: This input is
driven high to enable bus master writes.
EQ (6)
AMREN
Add-On bus Mastering Read ENable: This input is
driven high to enable bus master reads.
EQ (5)
FRC#
FIFO Read Clear: This line is driven low to clear the
PCI to Add-On FIFO.
EQ (4)
FWC#
FIFO Write Clear: This line is driven low to clear the
Add-On to PCI FIFO.
FRF (PCI to Add-On FIFO full) and FWE (Add-On to
PCI FIFO empty) supplement the RDEMPTY and
WRFULL status indicators. These additional status
outputs provide additional FIFO status information for
Add-On FIFO control logic.
Figure 10. Synchronous FIFO Register Burst RDFIFO# Access Example
Figure 9. Asynchronous FIFO Register RDFIFO# Access Example
DQ[31:0]
RDFIFO#
RDEMPTY
Valid Data Out
Status Before Read
New Status
FIFO Pointer Advances
BPCLK
DQ[31:0]
RDFIFO#
RDEMPTY
Data 1
Data 2
Data 0
FIFO Pointer Advances
Status Before Read
New Status
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