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参数资料
型号： S5933QE
厂商： APPLIEDMICRO INC
元件分类： 总线控制器
英文描述： PCI BUS CONTROLLER, PQFP160
封装： PLASTIC, QFP-160
文件页数： 32/176页
文件大小： 823K
代理商： S5933QE
3-140
PASS-THRU OVERVIEW
S5933
Pass-Thru Status/Control Signals
The S5933 Pass-Thru registers are accessed using
the standard Add-On register access pins. The Pass-
Thru Address Register (APTA) can, optionally, be ac-
cessed using a single, direct access input, PTADR#.
Pass-Thru cycle status indicators are provided to
control Add-On logic based on the type of Pass-Thru
access occurring (single cycle, burst, etc.). The fol-
lowing signals are provided for Pass-Thru operation:
Signal
Function
PTATN#
This output indicates a Pass-Thru
access is occurring
PTBURST#
This output indicates the Pass-Thru
access is a PCI burst access
PTNUM[1:0]
These outputs indicate which Pass-
Thru region decoded the PCI ad-
dress
PTBE[3:0]#
These outputs indicate which data
bytes are valid (PCI writes), or
requested (PCI reads)
PTWR
This output indicates if the Pass-
Thru access is a PCI read or a write
PTADR#
When asserted, this input drives the
Pass-Thru Address Register con-
tents onto the Add-On data bus
PTRDY#
When asserted, this input indicates
the current Pass-Thru transfer has
been completed by the Add-On
BPCLK
Buffered PCI bus clock output (to
synchronize Pass-Thru data register
accesses)
Pass-Thru Add-On Data Bus Sizing
Many applications require an 8-bit or 16-bit Add-On
bus interface. Pass-Thru regions can be configured
to support bus widths other than 32-bits. Each Pass-
Thru region can be defined, during initialization, as 8,
16-, or 32-bits. All of the regions do not need to be
the same. This feature allows a simple interface to 8-
and 16-bit Add-On devices.
To support alternate Add-On bus widths, the S5933
performs internal data bus steering. This allows the
Add-On interface to assemble and disassemble 32-
bit PCI data using multiple Add-On accesses to the
Pass-Thru Data Register (APTD). The Add-On byte
enable inputs (BE[3:0]#) are used to access the indi-
vidual bytes or words within APTD.
BUS INTERFACE
The Pass-Thru interface on the S5933 is a PCI tar-
get-only function. Pass-Thru operation allows PCI ini-
tiators to read or write resources on the Add-On card.
A PCI initiator may access the Add-On with single
data phase cycles or multiple data phase bursts.
The Add-On interface implements Pass-Thru status
and control signals used by logic to complete data
transfers initiated by the PCI bus. The Pass-Thru inter-
face is designed to allow Add-On logic to function with-
out knowledge of PCI bus activity. Add-On logic only
needs to react to the Pass-Thru status outputs. The
S5933 PCI interface independently interacts with the
PCI initiator to control data flow between the devices.
The following sections describe the PCI and Add-On
bus interfaces. The PCI interface description pro-
vides a basic overview of how the S5933 interacts
with the PCI bus, and may be useful in system de-
bugging. The Add-On interface description indicates
functions required by Add-On logic and details the
Pass-Thru handshaking protocol.
PCI Bus Interface
The S5933 decodes all PCI bus cycle addresses. If
the address associated with the current cycle is to
one of S5933 Pass-Thru regions, DEVSEL# is as-
serted. If the Pass-Thru logic is currently idle (not
busy finishing a previous Pass-Thru operation), the
bus cycle type is decoded and the Add-On Pass-Thru
status outputs are set to initiate a transfer on the
Add-On side. If the Pass-Thru logic is currently busy
completing a previous access, the S5933 signals a
retry to PCI initiator.
The following sections describe the behavior of the
PCI interface for Pass-Thru accesses to the S5933.
Single cycle accesses, burst accesses, and target-
initiated retries are detailed.
PCI Pass-Thru Single Cycle Accesses
Single cycle transfers are the simplest PCI bus trans-
action. Single cycle transfers have an address phase
and a single data phase. The PCI bus transaction
starts when an initiator drives address and command
information onto the PCI bus and asserts FRAME#.
The initiator always deasserts frame before the last
data phase. For single cycle transfers, FRAME# is
only asserted during the address phase (indicating
the first data phase is also the last).
When the S5933 sees FRAME# asserted, it samples
the address and command information to determine if
the bus transaction is intended for it. If the address is
within one of the defined Pass-Thru regions, the
S5933 accepts the transfer (assert DEVSEL#), and
stores the PCI address in the Pass-Thru Address
Register (APTA).
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