参数资料
型号: S5933QE
厂商: APPLIEDMICRO INC
元件分类: 总线控制器
英文描述: PCI BUS CONTROLLER, PQFP160
封装: PLASTIC, QFP-160
文件页数: 135/176页
文件大小: 823K
代理商: S5933QE
3-71
ADD-ON BUS OPERATION REGISTERS
S5933
ADD-ON CONTROLLED BUS MASTER
READ ADDRESS REGISTER (MRAR)
Register Name:
Master Read Address
Add-On Address Offset: 30h
Power-up value:
00000000h
Attribute:
Read/Write
Size:
32 bits
This register is only accessible when Add-On initiated
bus mastering is enabled.
This register is used to establish the PCI address for
data moving to the Add-On bus from the PCI bus
during PCI bus memory read operations. It consists
of a 30-bit counter with the low-order two bits
hardwired as zeros. Transfers may be any non-zero
byte length as defined by the transfer count register,
MRTC and must begin on a DWORD boundary. This
DWORD boundary starting constraint is placed upon
this controller’s PCI bus master transfers so that byte
lane alignment can be maintained between the
S5395X controller’s internal FIFO data path, the Add-
On interface and the PCI bus.
Note: Applications which require a non-DWORD
starting boundary will need to move the first few
bytes under software program control (and without
using the FIFO) to establish a DWORD boundary.
After the DWORD boundary is established the S5933
can begin the task of PCI bus master data transfers.
The Master Read Address Register is continually up-
dated during the transfer process and will always be
pointing to the next unread location. Reading of this
register during a transfer process (done when the
S5933 controller is functioning as a target—i.e., not a
bus master) is permitted and may be used to monitor
the progress of the transfer. During the address
phase for bus master read transfers, the two least
significant bits presented on the PCI bus AD[31:0]
will always be zero. This identifies to the target
memory that the burst address sequence will be in a
linear order rather than in an Intel 486 or Pentium
cache line fill sequence. Also, the PCI bus address
bit A1 will always be zero when this controller is the
bus master. This signifies to the target that the con-
troller is burst capable and that the target should not
arbitrarily disconnect after the first data phase of this
operation.
Under certain circumstances, MRAR can be ac-
cessed from the Add-On bus instead of the PCI bus.
31
0
1
0
2
Bit
Value
DWORD Address (RO)
Read Transfer Address (R/W)
Figure 2. Add-On Controlled Bus Master Read Address Register
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