![](http://datasheet.mmic.net.cn/140000/S5933QE_datasheet_5011649/S5933QE_81.png)
3-93
PCI BUS INTERFACE
S5933
Read accesses from the S5933 operation registers
(S5933 as a target) are shown in Figure 2. The
S5933 conditionally asserts STOP# in clock period 3
if the initiator keeps FRAME# asserted during clock
period 2 with IRDY# asserted (indicating a burst is
being attempted). Wait states may be added by the
initiator by not asserting the signal IRDY# during
clock 3 and beyond. If FRAME# remains asserted,
but IRDY# is not asserted, the initiator is just adding
wait states, not necessarily attempting a burst.
There is only one condition where accesses to S5933
operation registers do not return TRDY# but do as-
sert STOP#. This is called a target-initiated termina-
tion or target disconnect and occurs when a read
attempt is made to an empty S5933 FIFO. The asser-
tion of STOP# without the assertion of TRDY# indi-
cates that the initiator should retry the operation later.
When burst read transfers are attempted to the
S5933 operation registers, STOP# is asserted during
the first data transfer to indicate to the initiator that no
further transfers (data phases) are possible. This is a
target-initiated termination where the target discon-
nects after the first data transfer. Figure 3 shows the
signal relationships during a burst read attempt to the
S5933 operation registers.
Figure 2. Single Data Phase PCI Bus Read of S5933 Registers (S5933 as Target)
FRAME #
AD [31:0]
C/BE [3:0]#
IRDY#
TRDY#
DEVSEL#
STOP#
ADDRESS
DATA
BYTE ENABLES
BUS COMMAND
1
2
3
45
(I)
(T)
(I)
(T)
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
Figure 3. Burst PCI Bus Read Attempt to S5933 Registers (S5933 as Target)
PCI CLOCK
FRAME #
AD [31:0]
C/BE [3:0]#
IRDY#
TRDY#
DEVSEL#
STOP#
ADDRESS
DATA
BYTE ENABLES (1)
1
2
3
45
(I)
(T)
(I)
BE (2)
BUS COMMAND
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET