3-99
PCI BUS INTERFACE
S5933
Target Requested Retries
When the S5933 FIFO registers are accessed
(S5933 as a target) and data is unavailable (empty
FIFO) for read transfers or cannot be accepted for
write transfers (full FIFO), the S5933 immediately ter-
minates the cycle by requesting a retry. The S5933
also initiates a retry for Pass-Thru writes where the
Add-On has not completed the preceding Pass-Thru
write by asserting PTRDY#, and for Pass-Thru reads
where the Add-On cannot supply data within 8 PCI
clocks (16 clocks for the first data phase of a burst).
A retry is requested by a target asserting both
STOP# and DEVSEL# while TRDY# is deasserted.
Figure 11 shows the behavior of the S5933 when
performing a target-initiated retry.
Target Aborts
A target abort termination represents an error condi-
tion where no number of retries will produce a suc-
cessful target access. A target abort is uniquely
identified by the target deasserting DEVSEL# and
TRDY# while STOP# is asserted. When a target per-
forms an abort, it must also set bit 11 of its PCI
Status register. The S5933 configuration and opera-
tion registers never respond with a target abort when
accessed. If the S5933 encounters this condition
when operating as a PCI initiator, the S5933 sets bit
12 (received target abort) in the PCI Status register.
Figure 12 depicts a target abort cycle.
Target termination types are summarized in Table 2.
Termination
DEVSEL#
STOP# TRDY#
Comment
Disconnect
on
Data is transferred. Transaction needs to be re-initiated
to complete.
Retry
on
off
Data was not transferred.
Transaction should be tried later.
Abort
off
on
off
Data was not transferred. Fatal error.
Table 2. Target Termination Types
Figure 11. Target-Initiated Retry
PCI CLOCK
FRAME #
IRDY#
TRDY#
STOP#
DEVSEL#
1
2
3
INITIATOR
SEQUENCES IRDY#
+ FRAME# TO RETURN
TO IDLE STATE
45
TARGET
RETRY
SIGNALED
(T)
(I)
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET