- 您现在的位置：买卖IC网 > PDF目录98071 > S5933QE (APPLIEDMICRO INC) PCI BUS CONTROLLER, PQFP160 PDF资料下载
参数资料
| 型号： | S5933QE |
| 厂商： | APPLIEDMICRO INC |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封装： | PLASTIC, QFP-160 |
| 文件页数： | 27/176页 |
| 文件大小： | 823K |
| 代理商： | S5933QE |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页当前第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页
3-135
FIFO OVERVIEW
S5933
Some applications hold the RDFIFO# and WRFIFO#
inputs active for a synchronous interface. In 16-bit
mode, designs must avoid writing to a full FIFO. The
data for the write is lost, but the internal mechanism
to direct the 16-bit external data bus to the upper 16-
bits of the FIFO register is triggered. This creates a
situation where the FIFO is out of step. The next 16-
bit FIFO write is directed to the upper 16-bits of the
FIFO, and the FIFO advances incorrectly. The
WRFULL output should be used to gate the
WRFIFO# input to avoid this situation. A similar prob-
lem can occur if Add-On logic attempts to read an
empty FIFO in 16-bit mode. RDEMPTY should be
used to gate the RDFIFO# input to avoid problems
with the FIFO getting out of step. In 32-bit mode
(MODE = low), these situations do not occur.
If FIFO accesses are done without the direct access
signals with MODE configured for 16-bits (using
ADR, SELECT#, etc.), external hardware must toggle
ADR1 between consecutive 16-bit bus cycles. The
FIFO advance condition must be set to correspond to
the order the application accesses the upper and
lower words in the FIFO register.
CONFIGURATION
The FIFO configuration takes place during initialization
and during operation. During initialization, the FIFO
hardware interface method and bus master register
access rights are defined. During operation, FIFO ad-
vance conditions, endian conversion, and bus
mastering capabilities are defined. The following sec-
tion describes the bits and registers which are involved
with controlling and monitoring FIFO operation.
FIFO Setup During Initialization
Location 45h in an external non-volatile memory may
be used to configure the S5933 FIFO during initializa-
tion. If no external non-volatile memory is used, the
S5933 defaults to PCI initiated bus master transfers
with asynchronous operation for FIFO accesses.
The value of bit 7 in location 45h determines if the
address and transfer count registers used in bus
mastering are accessible from the PCI bus or from
the Add-On bus. Once the configuration information
is downloaded from non-volatile memory after reset,
the bus mastering initialization method can not be
changed. Access to the bus master address and
transfer count registers cannot be alternated between
the PCI bus and the Add-On interface during opera-
tion.
Bits 6 and 5 in location 45h determine if FIFO register
accesses using the RDFIFO#, WRFIFO#, RD# and
WR# inputs operate asynchronous or synchronous to
BPCLK. For asynchronous operation, RDFIFO#,
WRFIFO#, RD# and WR# operate as clocks for data.
For synchronous operation, RDFIFO#, WRFIFO#,
RD# and WR# operate as enables, using BPCLK to
clock data. Synchronous operation allows higher data
transfer rates.
Location 45h Configuration Bits
Bit 7
Bus Master Register Access
0
Address and transfer count registers only
accessible from the Add-On interface
1
Address and transfer count registers only
accessible from the PCI interface (default)
Bit 6
RDFIFO#, RD# Operation
0
Synchronous Mode - RDFIFO# and RD#
functions as enables
1
Asynchronous Mode - RDFIFO# and RD#
functions as clocks (default)
Bit 5
WRFIFO#, WR# Operation
0
Synchronous Mode - WRFIFO# and WR#
functions as enables
1
Asynchronous Mode - WRFIFO# and WR#
functions as clocks (default)
Bit 0
Target Latency Timer Enable
0
Disable PCI Latency Timer Time Out - Will
not disconnect with retry if cannot issue
TRDY in specified time
1
Enable PCI Latency Timer Time Out - Will be
PCI 2.1 compliant
FIFO Status and Control Bits
The FIFO status can be monitored and the FIFO op-
eration controlled from the PCI Operation Registers
and/or the Add-On Operation Registers. The FIFO
register resides at offset 20h in the PCI and Add-On
Operation Registers.
相关PDF资料 |
PDF描述 |
|---|---|
| S6A0032 | 16 X 80 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC138 |
| S6A0069 | 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC80 |
| S6A0078 | 34 X 120 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC183 |
| S80296SA40 | 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 |
| S80486-DX4-75-S-V-8-B | 32-BIT, 75 MHz, MICROPROCESSOR, PQFP208 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S5935 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935_07 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
发布紧急采购，3分钟左右您将得到回复。