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3-86
INITIALIZATION
S5933
PCI BUS CONFIGURATION CYCLES
Cycles beginning with the assertion IDSEL and
FRAME# along with the two configuration command
states for C/BE[3:0] (configuration read or write) ac-
cess an individual device’s configuration space. Dur-
ing the address phase of the configuration cycle just
described, the values of AD0 and AD1 identify if the
access is a Type 0 configuration cycle or a Type 1
configuration cycle. Type 0 cycles have AD0 and
AD1 equal to 0 and are used to access PCI bus
agents. Type 1 configuration cycles are intended only
for bridge devices and have AD0 as a 1 with AD1 as
a 0 during the address phase.
The S5933 PCI device is a bus agent (not a bridge)
and responds only to a Type 0 configuration ac-
cesses. Figure 5 depicts the state of the AD bus
during the address phase of a Type 0 configuration
access. The S5933 controller does not support the
multiple function numbers field (AD[10:8]) and only
responds to the all-zero function number value.
The configuration registers for the S5933 PCI control-
ler can only be accessed under the following
conditions:
IDSEL high (PCI slot unique signal which
identifies access to configuration registers)
along with FRAME# low.
Address bits A0 and A1 are 0 (Identifies a Type
0 configuration access).
Address bits A31-A11 are ignored.
Address bits A8, A9, and A10 are 0 (Function
number field of zero supported).
Command bits, C/BE[3:0]# must identify a
configuration cycle command (101X).
Figure 6 describes the signal timing relationships for
configuration read cycles. Figure 7 describes configu-
ration write cycles.
Figure 5. PCI AD Bus Definition During a Type 0 Configuration Access
FUNCTION
NUMBER
RESERVED
REGISTER
NUMBER
00
31
11
10
8
7
2
1
0
TYPE 0
00XXXXXX
-
INTERNAL REGISTER
ADDRESS
(DEVICE ID, ETC.)
ONLY 000 VALUE SUPPORTED BY THIS
DEVICE.