- 您现在的位置：买卖IC网 > PDF目录98071 > S5933QE (APPLIEDMICRO INC) PCI BUS CONTROLLER, PQFP160 PDF资料下载
参数资料
| 型号： | S5933QE |
| 厂商： | APPLIEDMICRO INC |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封装： | PLASTIC, QFP-160 |
| 文件页数： | 169/176页 |
| 文件大小： | 823K |
| 代理商： | S5933QE |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页当前第169页第170页第171页第172页第173页第174页第175页第176页
3-104
PCI BUS INTERFACE
S5933
PCI BUS INTERRUPTS
The S5933 controller is able to generate PCI bus inter-
rupts by asserting the PCI bus interrupt signal
(INTA#). INTA# is a multisourced, wire-ORed signal
on the PCI bus and is driven by an open drain output
on the S5933. The assertion and deassertion of INTA#
have no fixed timing relationship with respect to the
PCI bus clock. Once the S5933 asserts INTA#, it re-
mains asserted until the interrupt source is cleared by
a write to the Interrupt Control/Status Register
(INTCSR).
PCI BUS PARITY ERRORS
The PCI specification defines two error-reporting sig-
nals, PERR# and SERR#. These signals indicate a
parity error condition on the signals AD[31:0], C/
BE[3:0]#, and PAR. The validity of the PAR signal is
delayed one clock period from its corresponding
AD[31:0] and C/BE[3:0]# signals. Even parity exists
when the total number of ones in the group of signals
is equal to an even number. PERR# is the error-
reporting mechanism for parity errors that occur dur-
ing the data phase for all but PCI Special Cycle
commands. SERR# is the error-reporting mechanism
for parity errors that occur during the address phase.
The timing diagram in Figure 18 shows the timing
relationships between the signals AD[31:0], C/
BE[3:0]#, PAR, PERR# and SERR#.
The S5933 asserts SERR# if it detects odd parity
during an address phase, if enabled. The SERR#
enable bit is bit 8 in the S5933 PCI Command Regis-
ter. The odd parity error condition involves the state
of signals AD[31:0] and C/BE[3:0]# when FRAME# is
first asserted and the PAR signal during the following
clock. If an error is detected, the S5933 asserts
SERR# on the following (after PAR valid) clock.
Since many targets may observe an error on an ad-
dress phase, the SERR# signal is an open drain
multisourced, wire-ORed signal on the PCI bus. The
S5933 drives SERR# low for one clock period when
an address phase error is detected. Once an SERR
error is detected by the S5933, the PCI Status regis-
ter bit 14, System Error, is set and remains until
cleared through software or a hardware reset.
The PERR# signal is similar to the SERR# with two
differences: it reports errors for the data phase and is
only asserted by the device receiving the data. The
S5933 drives this signal (removed from tri-state)
when it is the selected target for write transactions or
when it is the current master for bus read transac-
tions. The parity error conditions are only reflected by
the PERR# pin if the Parity Error Enable bit (bit 6) of
the PCI Command register is set. Upon the detection
of a data parity error, the Detected Parity Error bit (bit
15) of the PCI Status Register is set. Unlike the
PERR# signal pin, this Status bit sets regardless of
the state of the PCI Command register Parity Error
Enable bit. An additional status bit (bit 8) called “Data
Parity Reported” of the PCI Status register is em-
ployed to report parity errors that occur when the
S5933 is the bus master. The “Data Parity Error Re-
ported” status requires that the Parity Error Enable bit
be set in the PCI Command register.
The assertion of PERR# occurs two clock periods
following the data transfer. This two-clock delay oc-
curs because the PAR signal does not become valid
until the clock following the transfer, and an addi-
tional clock is provided to generate and assert
PERR# once an error is detected. PERR# is only
asserted for one clock cycle for each error sensed.
The S5933 only qualifies the parity error detection
during the actual data transfer portion of a data
phase (when both IRDY# and TRDY# are asserted).
Figure 18. Error Reporting Signals
PCI CLOCK
FRAME
AD[31:0]
C/BE[3:0]#
PAR
SERR#
PERR#
12
3
5
4
6
8
7
9
ADDR
DATA
BYTE ENABLES
DATA
BE's
ADDR
A
AA
BB
CMD
READ TRANSACTION
GOOD
WRITE
TRANSACTION
B
A
B
A
B
ERROR
(T)
(I)
(T)
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
相关PDF资料 |
PDF描述 |
|---|---|
| S6A0032 | 16 X 80 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC138 |
| S6A0069 | 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC80 |
| S6A0078 | 34 X 120 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC183 |
| S80296SA40 | 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 |
| S80486-DX4-75-S-V-8-B | 32-BIT, 75 MHz, MICROPROCESSOR, PQFP208 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S5935 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935_07 | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全称:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
发布紧急采购，3分钟左右您将得到回复。