参数资料
型号: S5933QE
厂商: APPLIEDMICRO INC
元件分类: 总线控制器
英文描述: PCI BUS CONTROLLER, PQFP160
封装: PLASTIC, QFP-160
文件页数: 161/176页
文件大小: 823K
代理商: S5933QE
3-97
PCI BUS INTERFACE
S5933
Master Abort
PCI accesses to nonexistent or disabled targets
never observe DEVSEL# being asserted. In this situ-
ation, it is necessary for the initiator to abort the
transaction (master abort). As an initiator, S5933
waits for six clock periods after asserting FRAME# to
determine whether a master abort is required. These
six clock periods allow slow targets, which may re-
quire several bus clocks before being able to assert
DEVSEL#, to respond. It is also possible a PCI
bridge device is present which employs “subtractive”
decoding. A device which does a subtractive decode
asserts DEVSEL#, claiming the cycle, when it sees
that no other device has asserted it three clocks after
the address phase.
If DEVSEL# is not asserted, the S5933 deasserts
FRAME# (if asserted) upon the sixth clock period
(Figure 9). IRDY# is deasserted by the S5933 during
the next clock. The occurrence of a master abort
causes the S5933 to set bit 13 (Master Abort) of the
PCI Status Register, indicating an error condition.
Target-Initiated Termination
There are situations where the target may end a
transfer prematurely. This is called “target-initiated
termination.” Target terminations fall into three cat-
egories: disconnect, retry, and target abort. Only the
disconnect termination completes a data transfer.
Figure 9. Master Abort, No Response
PCI CLOCK
FRAME #
IRDY#
TRDY#
DEVSEL#
1
2
3
4
5
FAST
DEVICE
MEDIUM
DEVICE
SLOW
DEVICE
BRIDGE
DEVICE
(SUBTRACTIVE
DECODE)
67
8
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
(T)
(I)
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