19 UNIVERSAL SERIAL INTERFACE (USI) [S1C17564]
19-2
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
USI Pins
19.2
Table 19.2.1 lists the USI input/output pins.
2.1 List of USI Pins
Table 19.
Pin name
USI mode
Signal name
I/O
Function
US_SDI0
US_SDI1
UART
uart_rx
I
Data input pins
Inputs serial data sent from an external serial device.
SPI master
spi_sdi
I
I2C master
i2c_sda
I/O Data input/output pins
Inputs/outputs serial data from/to the I2C bus. (
*1)
I2C slave
i2c_sda
I/O
US_SDO0
US_SDO1
UART
uart_tx
O
Data output pins
Outputs serial data sent to an external serial device.
SPI master
spi_sdo
O
I2C master
–
Not used
I2C slave
–
US_SCK0
US_SCK1
UART
–
Not used
SPI master
spi_sck
O
Clock output pins
Outputs the SPI clock.
I2C master
i2c_scl
I/O SCL input/output pins
Inputs SCL line status from the I2C bus. Also outputs the I2C clock.
I2C slave
i2c_scl
I/O SCL input/output pins
Inputs SCL line status from the I2C bus. Also outputs a clock stretch
condition.
US_SSI0
US_SSI1
UART
–
Not used
SPI master
–
I2C master
i2c_sda
I/O Data input/output pins
Inputs/outputs serial data from/to the I2C bus. (
*1)
I2C slave
i2c_sda
I/O
*1: When USI Ch.x is configured to I2C master or slave mode, either the US_SDIx pin or the US_SSIx pin can be
used as the data input/output pin. Note, however, that both the US_SDIx and US_SSIx pins cannot be used as the
data input/output pin simultaneously.
Note: Use an I/O (P) port to output the slave select signal when USI Ch.x is configured to SPI master
mode.
The USI input/output pins (US_SDIx, US_SDOx, US_SCKx, US_SSIx) are shared with I/O ports and are initially
set as general-purpose I/O port pins. The pin functions must be switched using the port function select bits to use
the general purpose I/O port pins as USI input/output pins.
For detailed information on pin function switching, see the “I/O Ports (P)” chapter.
USI Clock Sources
19.3
Operating clock
The USI module uses PCLK as the operating clock. Therefore, PCLK must be supplied from the CLG before
starting the USI including setting the control registers. For more information on the PCLK supply, refer to the
“Clock Generator (CLG).”
Transfer clock
When the USI is configured to a UART, SPI master (normal mode), or I2C master device, the source clock for
transfer is supplied by the fine mode 16-bit timer (T16F). Program the T16F according to the transfer rate and
enable supplying the source clock to the USI module. The USI module divides the source clock to generate the
transfer clock (or sampling clock). Be aware that the division ratio in the USI depends on the interface mode.
When the USI is configured to an SPI master (fast mode) device, PCLK is used as the source clock.
When the USI is configured to an I2C slave device, the transfer clock is supplied from the external master de-
vice. However, I2C slave mode uses the T16F output clock to generate the sampling signal.