![](http://datasheet.mmic.net.cn/120000/S1C17564F00E10C_datasheet_3574343/S1C17564F00E10C_140.png)
15 UART
15-4
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
Count clock
Underflow signal (not corrected)
Underflow signal (corrected)
sclk (not corrected)
sclk (corrected)
Delayed
15
16
15
16
1
3.3 Delay Cycle Insertion in Fine Mode
Figure 15.
At initial reset, FMD[3:0] is set to 0x0, preventing insertion of delay cycles.
Note: Make sure the UART is halted (RXEN/UART_CTLx register = 0) before setting the baud rate gen-
erator.
Transfer Data Settings
15.4
Set the following conditions to configure the transfer data format.
Data length: 7 or 8 bits
Start bit:
Fixed at 1 bit
Stop bit:
1 or 2 bits
Parity bit:
Even, odd, or no parity
Note: Make sure the UART is halted (RXEN/UART_CTLx register = 0) before changing transfer data
format settings.
Data length
The data length is selected by CHLN/UART_MODx register. Setting CHLN to 0 (default) configures the data
length to 7 bits. Setting CHLN to 1 configures it to 8 bits.
Stop bit
The stop bit length is selected by STPB/UART_MODx register. Setting STPB to 0 (default) configures the stop
bit length to 1 bit. Setting STPB to 1 configures it to 2 bits.
Parity bit
Whether the parity function is enabled or disabled is selected by PREN/UART_MODx register. Setting PREN
to 0 (default) disables the parity function. In this case, no parity bit is added to the transfer data and the data is
not checked for parity when received. Setting PREN to 1 enables the parity function. In this case, a parity bit is
added to the transfer data and the data is checked for parity when received. When the parity function is enabled,
the parity mode is selected by PMD/UART_MODx register. Setting PMD to 0 (default) adds a parity bit and
checks for even parity. Setting PMD to 1 adds a parity bit and checks for odd parity.
Sampling clock (sclk)
CHLN = 0, PREN = 0, STPB = 0
CHLN = 0, PREN = 1, STPB = 0
CHLN = 0, PREN = 0, STPB = 1
CHLN = 0, PREN = 1, STPB = 1
CHLN = 1, PREN = 0, STPB = 0
CHLN = 1, PREN = 1, STPB = 0
CHLN = 1, PREN = 0, STPB = 1
CHLN = 1, PREN = 1, STPB = 1
s1
D0
D1
D2
D3
D4
D5
D6
s2
s1
D0
D1
D2
D3
D4
D5
D6
p
s2
s1
D0
D1
D2
D3
D4
D5
D6
s2
s3
s1
D0
D1
D2
D3
D4
D5
D6
p
s2
s3
s1
D0
D1
D2
D3
D4
D5
D6
D7
s2
s1
D0
D1
D2
D3
D4
D5
D6
D7
p
s2
s1
D0
D1
D2
D3
D4
D5
D6
D7
s2
s3
s1
D0
D1
D2
D3
D4
D5
D6
D7
p
s2
s3
s1: start bit, s2 & s3: stop bit, p: parity bit
Figure 15.4.1 Transfer Data Format