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APPENDIX A LIST OF I/O REGISTERS
AP-A-28
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
A/D Control/
Status Register
(ADC10_CTL)
0x5384
(16 bits)
D15
–
reserved
–
0 when being read.
D14–12 ADICH[2:0] Conversion channel indicator
0x0 to 0x3
0x0
R
D11
–
reserved
–
0 when being read.
D10
ADIBS
ADC10 status
1 Busy
0 Idle
0
R
D9
ADOWE
Overwrite error flag
1 Error
0 Normal
0
R/W Reset by writing 1.
D8
ADCF
Conversion completion flag
1 Completed 0 Run/Stand-
by
0
R Reset when ADC10_
ADD is read.
D7–6 –
reserved
–
0 when being read.
D5
ADOIE
Overwrite error interrupt enable
1 Enable
0 Disable
0
R/W
D4
ADCIE
Conversion completion int. enable 1 Enable
0 Disable
0
R/W
D3–2 –
reserved
–
0 when being read.
D1
ADCTL
A/D conversion control
1 Start
0 Stop
0
R/W
D0
ADEN
ADC10 enable
1 Enable
0 Disable
0
R/W
A/D Clock
Control Register
(ADC10_CLK)
0x5386
(16 bits)
D15–4 –
reserved
–
0 when being read.
D3–0 ADDF[3:0] A/D converter clock division ratio
select
ADDF[3:0]
Division ratio
0x0 R/W Source clock = PCLK
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
1/32768
1/16384
1/8192
1/4096
1/2048
1/1024
1/512
1/256
1/128
1/64
1/32
1/16
1/8
1/4
1/2
A/D Comparator
Setting Register
(ADC10_COM)
0x5388
(16 bits)
D15–6 –
reserved
–
0 when being read.
D5–4 FSEL[1:0]
A/D comparator adjustment
0x0 to 0x3
0x0 R/W
D3–2 –
reserved
–
0 when being read.
D1–0 XPD[1:0]
A/D comparator adjustment
0x0 to 0x3
0x3 R/W
0x5068, 0x5400–0x540c
16-bit PWM Timer Ch.0
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
T16A Clock
Control Register
Ch.0
(T16A_CLK0)
0x5068
(8 bits)
D7–4 CLKDIV
[3:0]
Clock division ratio select
CLKDIV[3:0]
Division ratio
0x0 R/W
OSC3 or
IOSC
OSC1
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
–
1/16384
1/8192
1/4096
1/2048
1/1024
1/512
1/256
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
–
1/256
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
D3–2 CLKSRC
[1:0]
Clock source select
CLKSRC[1:0]
Clock source
0x0 R/W
* S1C17564 only
0x3
0x2
0x1
0x0
External clock
OSC3
OSC1
IOSC*
D1
MULTIMD
Multi-comparator/capture mode
select
1 Multi
0 Normal
0
R/W
D0
CLKEN
Count clock enable
1 Enable
0 Disable
0
R/W
T16A Counter
Ch.0 Control
Register
(T16A_CTL0)
0x5400
(16 bits)
D15–6 –
reserved
–
0 when being read.
D5–4 CCABCNT
[1:0]
Counter select
CCABCNT[1:0] Counter Ch.
0x0 R/W
0x3
0x2
0x1
0x0
Ch.3
Ch.2
Ch.1
Ch.0
D3
CBUFEN
Compare buffer enable
1 Enable
0 Disable
0
R/W
D2
TRMD
Count mode select
1 One-shot
0 Repeat
0
R/W
D1
PRESET
Counter reset
1 Reset
0 Ignored
0
W 0 when being read.
D0
PRUN
Counter run/stop control
1 Run
0 Stop
0
R/W