19 UNIVERSAL SERIAL INTERFACE (USI) [S1C17564]
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
19-7
Sampling clock
TD[7:0]
Shift register
US_SDOx pin
UTBSY
UTDIF
Interrupt
start
stop
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0 parity
parity
BD0
Write
Transmit buffer empty interrupt
Reset by writing 1
Transmit buffer empty interrupt
(MSB first)
Data A
Data B
start BD7
BD6
5.1.1 Data Transmission Timing Chart (UART mode)
Figure 19.
Data reception
When the external serial device sends a start bit, the receiver circuit detects its low level and starts sampling the
following data bits. Once the 8-bit data has been received into the shift register, the received data is loaded into
the receive data buffer (RD[7:0]/USI_RDx register). If parity checking is enabled, the receiver circuit checks
the received data at the same time by checking the parity bit received immediately after the eighth data bit.
The receiver circuit includes two status flags: URDIF/USI_UIFx register and URBSY/USI_UIFx register.
The URDIF flag indicates the receive data buffer status. This flag is set to 1 indicating that the received data can
be read out when data received in the shift register is loaded to the receive data buffer. URDIF is an interrupt
flag. An interrupt request can be generated when this flag is set to 1 (see Section 19.7). Read the received data
from the receive data buffer using this interrupt. The receive data buffer size is 1 byte, therefore the received
data must be read before the subsequent data reception has completed. Furthermore, URDIF must be reset by
writing 1. If the subsequent receive data is written to the receive data buffer when URDIF is 1, an overrun error
occurs.
The URBSY flag indicates the shift register status. This flag is set to 1 while data is being received in the shift
register and reverts to 0 once the received data is loaded to the receive data buffer. Read this flag to check
whether the receiver circuit is operating or at standby.
Sampling clock
US_SDIx pin
Shift register
RD[7:0]
URBSY
URDIF
Interrupt
start
stop
AD7
parity
(MSB first)
Data A
Data B
Data C
start BD7
stop
parity
AD0
CD0
BD0
start CD7
Receive buffer full interrupt
Overrun error interrupt
(when Data B has not been read)
Read
Reset by writing 1
5.1.2 Data Receiving Timing Chart (UART mode)
Figure 19.
Data Transfer in SPI Master Mode
19.5.2
Data transmission
To start data transmission in SPI master mode, write the transmit data to the transmit data buffer (TD[7:0]/USI_
TDx register).
The buffer data is sent to the transmit shift register, and the module starts clock output from the US_SCKx pin.
The data in the shift register is shifted in sequence at the clock rising or falling edge (see Figure 19.4.5.1) and
sent from the US_SDOx pin.
The SPI controller includes two status flags for transfer control: STDIF/USI_SIFx register and SSIF/USI_SIFx
register.