19 UNIVERSAL SERIAL INTERFACE (USI) [S1C17564]
19-22
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
Interrupts in I
19.7.4
2C Slave Mode
The I2C slave mode includes a function for generating the following two different types of interrupts.
Operation completion interrupt
Receive error interrupt
Operation completion interrupt
To use this interrupt, set ISIE/USI_ISIEx register to 1. If ISIE is set to 0 (default), interrupt requests for this
cause will not be sent to the ITC.
When the operation that initiated by a software trigger has completed, the USI module sets ISIF/USI_ISIFx reg-
ister to 1. If operation completion interrupts are enabled (ISIE = 1), an interrupt request is sent simultaneously
to the ITC. An interrupt occurs if other interrupt conditions are met. You can inspect the ISSTA[2:0]/USI_ISIFx
register in the interrupt handler routine to determine the I2C operation/status that causes the interrupt.
7.4.1 I
Table 19.
2C Slave Status Bits
ISSTA[2:0]
Status
0x7
Reserved
0x6
NAK has been received.
0x5
ACK has been received.
0x4
ACK or NAK has been transmitted.
0x3
Receive data buffer is full.
0x2
Transmit data buffer is empty.
0x1
Stop condition has been detected.
0x0
Start condition has been detected.
(Default: 0x0)
Receive error interrupt
To use this interrupt, set ISEIE/USI_ISIEx register to 1. If ISEIE is set to 0 (default), interrupt requests for this
cause will not be sent to the ITC.
The USI module sets ISEIF/USI_ISIFx register to 1 if an overrun error is detected when receiving data. If re-
ceive error interrupts are enabled (ISEIE = 1), an interrupt request is sent simultaneously to the ITC. An inter-
rupt occurs if other interrupt conditions are met. You can inspect the ISEIF flags in the interrupt handler routine
to determine whether the USI (I2C slave mode) interrupt was caused by a receive error. If ISEIF is 1, the inter-
rupt handler routine will proceed with error recovery.
Control Register Details
19.8
8.1 List of USI Registers
Table 19.
Address
Register name
Function
0x50c0
USI_GCFG0 USI Ch.0 Global Configuration Register
Sets interface and MSB/LSB mode.
0x50c1
USI_TD0
USI Ch.0 Transmit Data Buffer Register
Transmit data buffer
0x50c2
USI_RD0
USI Ch.0 Receive Data Buffer Register
Receive data buffer
0x50c3
USI_UCFG0 USI Ch.0 UART Mode Configuration Register
Sets UART transfer conditions.
0x50c4
USI_UIE0
USI Ch.0 UART Mode Interrupt Enable Register
Enables interrupts.
0x50c5
USI_UIF0
USI Ch.0 UART Mode Interrupt Flag Register
Indicates interrupt occurrence status.
0x50c6
USI_SCFG0 USI Ch.0 SPI Master Mode Configuration Register
Sets SPI transfer conditions.
0x50c7
USI_SIE0
USI Ch.0 SPI Master Mode Interrupt Enable Register
Enables interrupts.
0x50c8
USI_SIF0
USI Ch.0 SPI Master Mode Interrupt Flag Register
Indicates interrupt occurrence status.
0x50c9
USI_SMSK0 USI Ch.0 SPI Master Mode Receive Data Mask Register
Sets receive data mask.
0x50ca
USI_IMTG0
USI Ch.0 I2C Master Mode Trigger Register
Starts I2C master operations.
0x50cb
USI_IMIE0
USI Ch.0 I2C Master Mode Interrupt Enable Register
Enables interrupts.
0x50cc
USI_IMIF0
USI Ch.0 I2C Master Mode Interrupt Flag Register
Indicates interrupt occurrence status.
0x50cd
USI_ISTG0
USI Ch.0 I2C Slave Mode Trigger Register
Starts I2C slave operations.
0x50ce
USI_ISIE0
USI Ch.0 I2C Slave Mode Interrupt Enable Register
Enables interrupts.
0x50cf
USI_ISIF0
USI Ch.0 I2C Slave Mode Interrupt Flag Register
Indicates interrupt occurrence status.
0x50e0
USI_GCFG1 USI Ch.1 Global Configuration Register
Sets interface and MSB/LSB mode.
0x50e1
USI_TD1
USI Ch.1 Transmit Data Buffer Register
Transmit data buffer
0x50e2
USI_RD1
USI Ch.1 Receive Data Buffer Register
Receive data buffer
0x50e3
USI_UCFG1 USI Ch.1 UART Mode Configuration Register
Sets UART transfer conditions.
0x50e4
USI_UIE1
USI Ch.1 UART Mode Interrupt Enable Register
Enables interrupts.
0x50e5
USI_UIF1
USI Ch.1 UART Mode Interrupt Flag Register
Indicates interrupt occurrence status.