APPENDIX A LIST OF I/O REGISTERS
AP-A-18
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
USI Ch.1 SPI
Master Mode
Receive Data
Mask Register
(USI_SMSK1)
0x50e9
(8 bits)
D7–0 SMSK[7:0] Receive data mask bit
SMSK7 = MSB
SMSK0 = LSB
0x0 to 0xff
0x0 R/W
USI Ch.1 I2C
Master Mode
Trigger Register
(USI_IMTG1)
0x50ea
(8 bits)
D7–5 –
reserved
–
0 when being read.
D4
IMTG
I2C master operation trigger
1 Trigger
0 Ignored
0
W
1 Waiting
0 Finished
R
D3
–
reserved
–
0 when being read.
D2–0 IMTGMOD
[2:0]
I2C master trigger mode select
IMTGMOD[2:0] Trigger mode
0x0 R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
Receive ACK/NAK
Transmit NAK
Transmit ACK
Receive data
Transmit data
Stop condition
Start condition
USI Ch.1 I2C
Master Mode
Interrupt Enable
Register
(USI_IMIE1)
0x50eb
(8 bits)
D7–2 –
reserved
–
0 when being read.
D1
IMEIE
Receive error interrupt enable
1 Enable
0 Disable
0
R/W
D0
IMIE
Operation completion int. enable
1 Enable
0 Disable
0
R/W
USI Ch.1 I2C
Master Mode
Interrupt Flag
Register
(USI_IMIF1)
0x50ec
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5
IMBSY
I2C master busy flag
1 Busy
0 Standby
0
R
D4–2 IMSTA[2:0] I2C master status
IMSTA[2:0]
Status
0x0
R
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
NAK received
ACK received
ACK/NAK sent
Rx buffer full
Tx buffer empty
Stop generated
Start generated
D1
IMEIF
Overrun error flag
1 Error
0 Normal
0
R/W Reset by writing 1.
D0
IMIF
Operation completion flag
1 Completed 0 Not completed
0
R/W
USI Ch.1 I2C
Slave Mode
Trigger Register
(USI_ISTG1)
0x50ed
(8 bits)
D7–5 –
reserved
–
0 when being read.
D4
ISTG
I2C slave operation trigger
1 Trigger
0 Ignored
0
W
1 Waiting
0 Finished
R
D3
–
reserved
–
0 when being read.
D2–0 ISTGMOD
[2:0]
I2C slave trigger mode select
ISTGMOD[2:0] Trigger mode
0x0 R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
Receive ACK/NAK
Transmit NAK
Transmit ACK
Receive data
Transmit data
reserved
Wait for start
USI Ch.1 I2C
Slave Mode
Interrupt Enable
Register
(USI_ISIE1)
0x50ee
(8 bits)
D7–2 –
reserved
–
0 when being read.
D1
ISEIE
Receive error interrupt enable
1 Enable
0 Disable
0
R/W
D0
ISIE
Operation completion int. enable
1 Enable
0 Disable
0
R/W
USI Ch.1 I2C
Slave Mode
Interrupt Flag
Register
(USI_ISIF1)
0x50ef
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5
ISBSY
I2C slave busy flag
1 Busy
0 Standby
0
R
D4–2 ISSTA[2:0] I2C slave status
ISSTA[2:0]
Status
0x0
R
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
NAK received
ACK received
ACK/NAK sent
Rx buffer full
Tx buffer empty
Stop detected
Start detected
D1
ISEIF
Overrun error flag
1 Error
0 Normal
0
R/W Reset by writing 1.
D0
ISIF
Operation completion flag
1 Completed 0 Not completed
0
R/W