19 UNIVERSAL SERIAL INTERFACE (USI) [S1C17564]
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
19-23
0x50e6
USI_SCFG1 USI Ch.1 SPI Master Mode Configuration Register
Sets SPI transfer conditions.
0x50e7
USI_SIE1
USI Ch.1 SPI Master Mode Interrupt Enable Register
Enables interrupts.
0x50e8
USI_SIF1
USI Ch.1 SPI Master Mode Interrupt Flag Register
Indicates interrupt occurrence status.
0x50e9
USI_SMSK1 USI Ch.1 SPI Master Mode Receive Data Mask Register
Sets receive data mask.
0x50ea
USI_IMTG1
USI Ch.1 I2C Master Mode Trigger Register
Starts I2C master operations.
0x50eb
USI_IMIE1
USI Ch.1 I2C Master Mode Interrupt Enable Register
Enables interrupts.
0x50ec
USI_IMIF1
USI Ch.1 I2C Master Mode Interrupt Flag Register
Indicates interrupt occurrence status.
0x50ed
USI_ISTG1
USI Ch.1 I2C Slave Mode Trigger Register
Starts I2C slave operations.
0x50ee
USI_ISIE1
USI Ch.1 I2C Slave Mode Interrupt Enable Register
Enables interrupts.
0x50ef
USI_ISIF1
USI Ch.1 I2C Slave Mode Interrupt Flag Register
Indicates interrupt occurrence status.
The USI registers are described in detail below. These are 8-bit registers.
Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1.
USI Ch.x Global Configuration Registers (USI_GCFGx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
USI Ch.x Global
Configuration
Register
(USI_GCFGx)
0x50c0
0x50e0
(8 bits)
D7–4 –
reserved
–
0 when being read.
D3
LSBFST
MSB/LSB first mode select
1 MSB first
0 LSB first
0
R/W
D2–0 USIMOD
[2:0]
Interface mode configuration
USIMOD[2:0]
I/F mode
0x0 R/W
0x7–0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
I2C slave
I2C master
reserved
SPI master
UART
Software reset
Note: This register must be configured before setting other USI registers.
D[7:4]
Reserved
D3
LSBFST: MSB/LSB First Mode Select Bit
Selects whether serial data will be transferred from the MSB or LSB.
1 (R/W): MSB first
0 (R/W): LSB first (default)
This setting affects all interface modes.
D[2:0]
USIMOD[2:0]: Interface Mode Configuration Bits
Selects an interface mode.
8.2 Interface Mode Selection
Table 19.
USIMOD[2:0]
Interface mode
0x7–0x6
Reserved
0x5
I2C slave
0x4
I2C master
0x3
Reserved
0x2
SPI master
0x1
UART
0x0
Software reset
(Default: 0x0)
Perform software reset (set USIMOD[2:0] to 0x0) and then set the interface mode before changing
other USI configurations.
USI Ch.x Transmit Data Buffer Registers (USI_TDx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
USI Ch.x
Transmit Data
Buffer Register
(USI_TDx)
0x50c1
0x50e1
(8 bits)
D7–0 TD[7:0]
USI transmit data buffer
TD7 = MSB
TD0 = LSB
0x0 to 0xff
0x0 R/W
D[7:0]
TD[7:0]: USI Transmit Data Buffer Bits
Sets transmit data to be written to the transmit data buffer. (Default: 0x0)