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19 UNIVERSAL SERIAL INTERFACE (USI) [S1C17564]
19-14
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
(1) Generating start condition
The procedure is the same as that of data transmission in I2C master mode.
(2) Sending slave address and transfer direction bit
The procedure is the same as that of data transmission in I2C master mode. However, send the slave address
with the transfer direction bit set to 1. Then check that the slave device sends back an ACK.
(3) Data reception
To start data reception, set IMTGMOD[2:0] to 0x3 and write 1 to IMTG.
This trigger starts outputting 8 clocks from the US_SCKx pin. The US_SDOx pin status is sampled in sync
with the clock and loaded to the shift register. The received data is loaded to the receive data buffer (RD[7:0]/
USI_RDx register) once the 8-bit data has been received in the shift register.
Writing 1 to IMTG sets IMBSY to 1. When the received data is loaded to the receive data buffer, IMBSY
reverts to 0 and IMSTA[2:0] is set to 0x3 (receive data buffer full). An interrupt request can be generated at
this point. Read the received data from the receive data buffer using this interrupt.
It is necessary to send back an ACK or NAK to the slave device after an 8-bit data has been received. To
send back an ACK, set IMTGMOD[2:0] to 0x4 and write 1 to IMTG. To send back a NAK, set IMTG-
MOD[2:0] to 0x5 and write 1 to IMTG.
IMBSY is set to 1 while an ACK/NAK is being sent and it reverts to 0 when the transmission has complet-
ed. An interrupt request can be generated at this point. When an ACK or NAK has been sent, IMSTA[2:0] is
set to 0x4.
Repeat an 8-bit data reception and ACK (NAK) transmission for the required number of times.
(4) Generating stop condition
The procedure is the same as that of data transmission in I2C master mode.
(5) Generating repeated start condition
The procedure is the same as that of data transmission in I2C master mode.
Clock stretch function
During transmitting/receiving data, the slave device may issue a wait request to the master device by pulling
down the SCL line to low until the slave device becomes ready to transmit/receive the subsequent data. The
master device enters a standby state until the wait request is canceled (the SCL line goes high).
This I2C controller supports this clock stretch function. When a clock stretch condition is detected after a slave
address or data has been sent/received, this module enters a waiting status and it does not start operating even if
it accepts a trigger for data transfer until the clock stretch status is canceled. IMBSY is maintained at 1 until the
triggered operation has completed including a waiting status.
US_SCKx pin (master output)
US_SCKx pin (slave output)
Clock stretch
5.3.10 Clock Stretch
Figure 19.
Control method in I2C slave mode
Data transfer in I2C slave mode is controlled using ISTGMOD[2:0]/USI_ISTGx register and ISTG/USI_ISTGx
register. Select an I2C slave operation using ISTGMOD[2:0] and write 1 to ISTG as the trigger. The I2C con-
troller controls the I2C bus to generate the specified operating status.