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APPENDIX A LIST OF I/O REGISTERS
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
AP-A-17
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
USI Ch.0 I2C
Slave Mode
Interrupt Enable
Register
(USI_ISIE0)
0x50ce
(8 bits)
D7–2 –
reserved
–
0 when being read.
D1
ISEIE
Receive error interrupt enable
1 Enable
0 Disable
0
R/W
D0
ISIE
Operation completion int. enable
1 Enable
0 Disable
0
R/W
USI Ch.0 I2C
Slave Mode
Interrupt Flag
Register
(USI_ISIF0)
0x50cf
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5
ISBSY
I2C slave busy flag
1 Busy
0 Standby
0
R
D4–2 ISSTA[2:0] I2C slave status
ISSTA[2:0]
Status
0x0
R
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
NAK received
ACK received
ACK/NAK sent
Rx buffer full
Tx buffer empty
Stop detected
Start detected
D1
ISEIF
Overrun error flag
1 Error
0 Normal
0
R/W Reset by writing 1.
D0
ISIF
Operation completion flag
1 Completed 0 Not completed
0
R/W
0x50e0–0x50ef
USI Ch.1
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
USI Ch.1 Global
Configuration
Register
(USI_GCFG1)
0x50e0
(8 bits)
D7–4 –
reserved
–
0 when being read.
D3
LSBFST
MSB/LSB first mode select
1 MSB first
0 LSB first
0
R/W
D2–0 USIMOD
[2:0]
Interface mode configuration
USIMOD[2:0]
I/F mode
0x0 R/W
0x7–0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
I2C slave
I2C master
reserved
SPI master
UART
Software reset
USI Ch.1
Transmit Data
Buffer Register
(USI_TD1)
0x50e1
(8 bits)
D7–0 TD[7:0]
USI transmit data buffer
TD7 = MSB
TD0 = LSB
0x0 to 0xff
0x0 R/W
USI Ch.1
Receive Data
Buffer Register
(USI_RD1)
0x50e2
(8 bits)
D7–0 RD[7:0]
USI receive data buffer
RD7 = MSB
RD0 = LSB
0x0 to 0xff
0x0
R
USI Ch.1
UART Mode
Configuration
Register
(USI_UCFG1)
0x50e3
(8 bits)
D7–4 –
reserved
–
0 when being read.
D3
UCHLN
Character length select
1 8 bits
0 7 bits
0
R/W
D2
USTPB
Stop bit select
1 2 bits
0 1 bit
0
R/W
D1
UPMD
Parity mode select
1 Even
0 Odd
0
R/W
D0
UPREN
Parity enable
1 With parity
0 No parity
0
R/W
USI Ch.1 UART
Mode Interrupt
Enable Register
(USI_UIE1)
0x50e4
(8 bits)
D7–3 –
reserved
–
0 when being read.
D2
UEIE
Receive error interrupt enable
1 Enable
0 Disable
0
R/W
D1
URDIE
Receive buffer full interrupt enable 1 Enable
0 Disable
0
R/W
D0
UTDIE
Transmit buffer empty int. enable
1 Enable
0 Disable
0
R/W
USI Ch.1 UART
Mode Interrupt
Flag Register
(USI_UIF1)
0x50e5
(8 bits)
D7
–
reserved
–
0 when being read.
D6
URBSY
Receive busy flag
1 Busy
0 Idle
0
R
D5
UTBSY
Transmit busy flag
1 Busy
0 Idle
0
R
D4
UPEIF
Parity error flag
1 Error
0 Normal
0
R/W Reset by writing 1.
D3
USEIF
Framing error flag
1 Error
0 Normal
0
R/W
D2
UOEIF
Overrun error flag
1 Error
0 Normal
0
R/W
D1
URDIF
Receive buffer full flag
1 Full
0 Not full
0
R/W
D0
UTDIF
Transmit buffer empty flag
1 Empty
0 Not empty
0
R/W
USI Ch.1 SPI
Master Mode
Configuration
Register
(USI_SCFG1)
0x50e6
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5
SCMD
Command bit (for 9-bit data)
1 High
0 Low
0
R/W
D4
SCHLN
Character length select
1 9 bits
0 8 bits
0
R/W
D3
SCPHA
Clock phase select
1 Phase 1
0 Phase 0
0
R/W
D2
SCPOL
Clock polarity select
1 Active L
0 Active H
0
R/W
D1
SMSKEN
Receive data mask enable
1 Enable
0 Disable
0
R/W
D0
SFSTMOD Fast mode select
1 Fast
0 Normal
0
R/W
USI Ch.1 SPI
Master Mode
Interrupt
Enable Register
(USI_SIE1)
0x50e7
(8 bits)
D7–3 –
reserved
–
0 when being read.
D2
SEIE
Receive error interrupt enable
1 Enable
0 Disable
0
R/W
D1
SRDIE
Receive buffer full interrupt enable 1 Enable
0 Disable
0
R/W
D0
STDIE
Transmit buffer empty int. enable
1 Enable
0 Disable
0
R/W
USI Ch.1 SPI
Master Mode
Interrupt Flag
Register
(USI_SIF1)
0x50e8
(8 bits)
D7–4 –
reserved
–
0 when being read.
D3
SSIF
Transfer busy flag
1 Busy
0 Idle
0
R
D2
SEIF
Overrun error flag
1 Error
0 Normal
0
R/W Reset by writing 1.
D1
SRDIF
Receive buffer full flag
1 Full
0 Not full
0
R/W
D0
STDIF
Transmit buffer empty flag
1 Empty
0 Not empty
0
R/W