9 16-BIT TIMERS (T16)
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
9-7
Setting TRMD to 0 sets the timer to repeat mode. In this mode, once the count starts, the timer contin-
ues to run until stopped by the application program. When the counter underflows, the timer presets the
counter to the reload data register value and continues the count. Thus, the timer periodically outputs an
underflow pulse. Set the timer to this mode to generate periodic interrupts or A/D conversion triggers at
desired intervals or to generate a serial transfer clock.
Setting TRMD to 1 sets the timer to one-shot mode. In this mode, the 16-bit timer stops automatically
as soon as the counter underflows. This means only one interrupt can be generated after the timer starts.
Note that the timer presets the counter to the reload data register value, then stops when an underflow
occurs. Set the timer to this mode to set a specific wait time.
D[3:2]
Reserved
D1
PRESER: Timer Reset Bit
Resets the timer.
1 (W):
Reset
0 (W):
Ignored
0 (R):
Always 0 when read (default)
Writing 1 to this bit presets the counter to the reload data value.
D0
PRUN: Timer Run/Stop Control Bit
Controls the timer RUN/STOP.
1 (R/W): Run
0 (R/W): Stop (default)
The timer starts counting when PRUN is written as 1 and stops when written as 0. When the timer is
stopped, the counter data is retained until reset or until the next RUN state.
T16 Ch.x Interrupt Control Registers (T16_INTx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
T16 Ch.x Inter-
rupt Control
Register
(T16_INTx)
0x4228
0x4248
0x4268
(16 bits)
D15–9 –
reserved
–
0 when being read.
D8
T16IE
T16 interrupt enable
1 Enable
0 Disable
0
R/W
D7–1 –
reserved
–
0 when being read.
D0
T16IF
T16 interrupt flag
1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.
D[15:9]
Reserved
D8
T16IE: T16 Interrupt Enable Bit
Enables or disables interrupts caused by counter underflows for each channel.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
Setting T16IE to 1 enables T16 interrupt requests to the ITC; setting to 0 disables interrupts.
D[7:1]
Reserved
D0
T16IF: T16 Interrupt Flag Bit
Indicates whether the cause of counter underflow interrupt has occurred or not.
1 (R):
Cause of interrupt has occurred
0 (R):
No cause of interrupt has occurred (default)
1 (W):
Flag is reset
0 (W):
Ignored
T16IF is the T16 module interrupt flag that is set to 1 when the counter underflows.
T16IF is reset by writing 1.