7 CLOCK GENERATOR (CLG)
7-10
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
Clock frequency selection
Three different clock output frequencies can be selected when OSC3 or IOSC is used as the clock source. Se-
lect the division ratio for the source clock using FOUTAD[1:0]/CLG_FOUTA register or FOUTBD[1:0]/CLG_
FOUTB register.
7.2 IOSC/OSC3 Division Ratio Selection
Table 7.
FOUTAD[1:0]/FOUTBD[1:0]
Division ratio
0x3
Reserved
0x2
1/4
0x1
1/2
0x0
1/1
(Default: 0x0)
Clock output control
The clock output is controlled using FOUTAE/CLG_FOUTA register or FOUTBE/CLG_FOUTB register. Set-
ting FOUTAE/FOUTBE to 1 outputs the FOUTA/FOUTB clock from the FOUTA/FOUTB pin. Setting it to 0
disables output.
FOUTAE (FOUTBE)
FOUTA (FOUTB) output
00
1
7.2 FOUTA/FOUTB Output
Figure 7.
Note: Since the FOUTA/FOUTB signal is not synchronized with FOUTAE/FOUTBE writing, switching
output on or off will generate certain hazards.
Control Register Details
7.8
8.1 List of CLG Registers
Table 7.
Address
Register name
Function
0x5060
CLG_SRC
Clock Source Select Register
Selects the clock source.
0x5061
CLG_CTL
Oscillation Control Register
Controls oscillation.
0x5062
CLG_NFEN
Noise Filter Enable Register
Turns oscillation stabilization wait circuit/noise filter on/off.
0x5064
CLG_FOUTA
FOUTA Control Register
Controls FOUTA clock output.
0x5065
CLG_FOUTB
FOUTB Control Register
Controls FOUTB clock output.
0x506e
CLG_IOSC
IOSC Control Register
Configures IOSC oscillation frequency.
0x5080
CLG_PCLK
PCLK Control Register
Controls the PCLK supply.
0x5081
CLG_CCLK
CCLK Control Register
Configures the CCLK division ratio.
The CLG module registers are described in detail below. These are 8-bit registers.
Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1.
Clock Source Select Register (CLG_SRC)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Clock Source
Select Register
(CLG_SRC)
S1C17554
0x5060
(8 bits)
D7–2 –
reserved
–
0 when being read.
D1–0 CLKSRC[1:0] System clock source select
CLKSRC[1:0]
Clock source
0x2 R/W
0x3
0x2
0x1
0x0
reserved
OSC3
OSC1
reserved
Clock Source
Select Register
(CLG_SRC)
S1C17564
0x5060
(8 bits)
D7–2 –
reserved
–
0 when being read.
D1–0 CLKSRC[1:0] System clock source select
CLKSRC[1:0]
Clock source
0x0 R/W
0x3
0x2
0x1
0x0
reserved
OSC3
OSC1
IOSC
D[7:2]
Reserved