8 I/O PORTS (P)
8-10
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
Px Port Chattering Filter Control Registers (Px_CHAT)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Px Port
Chattering
Filter Control
Register
(Px_CHAT)
0x5208
0x5218
0x5228
0x5238
0x5248
0x5258
(8 bits)
D7
–
reserved
–
0 when being read.
D6–4 PxCF2[2:0] Px[7:4] chattering filter time select
PxCF2[2:0]
Filter time
0x0 R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
16384/fPCLK
8192/fPCLK
4096/fPCLK
2048/fPCLK
1024/fPCLK
512/fPCLK
256/fPCLK
None
D3
–
reserved
–
0 when being read.
D2–0 PxCF1[2:0] Px[3:0] chattering filter time select
PxCF1[2:0]
Filter time
0x0 R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
16384/fPCLK
8192/fPCLK
4096/fPCLK
2048/fPCLK
1024/fPCLK
512/fPCLK
256/fPCLK
None
Note: P0CF1[2:0] only are available for the P0 ports. Other bits are reserved and always read as 0.
D7
Reserved
D[6:4]
PxCF2[2:0]: Px[7:4] Chattering Filter Time Select Bits
Configures the chattering filter circuit for the Px[7:4] ports.
D3
Reserved
D[2:0]
PxCF1[2:0]: Px[3:0] Chattering Filter Time Select Bits
Configures the chattering filter circuit for the Px[3:0] ports.
The I/O ports include a chattering filter circuit for key entry that can be disabled or enabled with
a check time specified individually for the four Px[3:0] and Px[7:4] ports using PxCF1[2:0] and
PxCF2[2:0], respectively.
8.2 Chattering Filter Function Settings
Table 8.
PxCF1[2:0]/PxCF2[2:0]
Check time *
0x7
16384/fPCLK (8 ms)
0x6
8192/fPCLK (4 ms)
0x5
4096/fPCLK (2 ms)
0x4
2048/fPCLK (1 ms)
0x3
1024/fPCLK (512 s)
0x2
512/fPCLK (256 s)
0x1
256/fPCLK (128 s)
0x0
No check time (off)
(Default: 0x0,
* when PCLK = 2 MHz)
Notes: The chattering filter check time refers to the maximum pulse width that can be filtered. Gen-
erating an input interrupt requires a minimum input time of the check time and a maximum
input time of twice the check time.
The Px port interrupt must be disabled before setting the Px_CHAT register. Setting the reg-
ister while the interrupt is enabled may generate inadvertent Px interrupt. Also the chattering
filter circuit requires a maximum of twice the check time for stabilizing the operation status.
Before enabling the interrupt, make sure that the stabilization time has elapsed.
P0 Port Key-Entry Reset Configuration Register (P0_KRST)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
P0 Port Key-
Entry Reset
Configuration
Register
(P0_KRST)
0x5209
(8 bits)
D7–2 –
reserved
–
0 when being read.
D1–0 P0KRST[1:0] P0 port key-entry reset
configuration
P0KRST[1:0]
Configuration 0x0 R/W
0x3
0x2
0x1
0x0
P0[3:0]
P0[2:0]
P0[1:0]
Disable