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APPENDIX A LIST OF I/O REGISTERS
AP-A-16
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
USI Ch.0 UART
Mode Interrupt
Flag Register
(USI_UIF0)
0x50c5
(8 bits)
D7
–
reserved
–
0 when being read.
D6
URBSY
Receive busy flag
1 Busy
0 Idle
0
R
D5
UTBSY
Transmit busy flag
1 Busy
0 Idle
0
R
D4
UPEIF
Parity error flag
1 Error
0 Normal
0
R/W Reset by writing 1.
D3
USEIF
Framing error flag
1 Error
0 Normal
0
R/W
D2
UOEIF
Overrun error flag
1 Error
0 Normal
0
R/W
D1
URDIF
Receive buffer full flag
1 Full
0 Not full
0
R/W
D0
UTDIF
Transmit buffer empty flag
1 Empty
0 Not empty
0
R/W
USI Ch.0 SPI
Master Mode
Configuration
Register
(USI_SCFG0)
0x50c6
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5
SCMD
Command bit (for 9-bit data)
1 High
0 Low
0
R/W
D4
SCHLN
Character length select
1 9 bits
0 8 bits
0
R/W
D3
SCPHA
Clock phase select
1 Phase 1
0 Phase 0
0
R/W
D2
SCPOL
Clock polarity select
1 Active L
0 Active H
0
R/W
D1
SMSKEN
Receive data mask enable
1 Enable
0 Disable
0
R/W
D0
SFSTMOD Fast mode select
1 Fast
0 Normal
0
R/W
USI Ch.0 SPI
Master Mode
Interrupt
Enable Register
(USI_SIE0)
0x50c7
(8 bits)
D7–3 –
reserved
–
0 when being read.
D2
SEIE
Receive error interrupt enable
1 Enable
0 Disable
0
R/W
D1
SRDIE
Receive buffer full interrupt enable 1 Enable
0 Disable
0
R/W
D0
STDIE
Transmit buffer empty int. enable
1 Enable
0 Disable
0
R/W
USI Ch.0 SPI
Master Mode
Interrupt Flag
Register
(USI_SIF0)
0x50c8
(8 bits)
D7–4 –
reserved
–
0 when being read.
D3
SSIF
Transfer busy flag
1 Busy
0 Idle
0
R
D2
SEIF
Overrun error flag
1 Error
0 Normal
0
R/W Reset by writing 1.
D1
SRDIF
Receive buffer full flag
1 Full
0 Not full
0
R/W
D0
STDIF
Transmit buffer empty flag
1 Empty
0 Not empty
0
R/W
USI Ch.0 SPI
Master Mode
Receive Data
Mask Register
(USI_SMSK0)
0x50c9
(8 bits)
D7–0 SMSK[7:0] Receive data mask bit
SMSK7 = MSB
SMSK0 = LSB
0x0 to 0xff
0x0 R/W
USI Ch.0 I2C
Master Mode
Trigger Register
(USI_IMTG0)
0x50ca
(8 bits)
D7–5 –
reserved
–
0 when being read.
D4
IMTG
I2C master operation trigger
1 Trigger
0 Ignored
0
W
1 Waiting
0 Finished
R
D3
–
reserved
–
0 when being read.
D2–0 IMTGMOD
[2:0]
I2C master trigger mode select
IMTGMOD[2:0] Trigger mode
0x0 R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
Receive ACK/NAK
Transmit NAK
Transmit ACK
Receive data
Transmit data
Stop condition
Start condition
USI Ch.0 I2C
Master Mode
Interrupt Enable
Register
(USI_IMIE0)
0x50cb
(8 bits)
D7–2 –
reserved
–
0 when being read.
D1
IMEIE
Receive error interrupt enable
1 Enable
0 Disable
0
R/W
D0
IMIE
Operation completion int. enable
1 Enable
0 Disable
0
R/W
USI Ch.0 I2C
Master Mode
Interrupt Flag
Register
(USI_IMIF0)
0x50cc
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5
IMBSY
I2C master busy flag
1 Busy
0 Standby
0
R
D4–2 IMSTA[2:0] I2C master status
IMSTA[2:0]
Status
0x0
R
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
NAK received
ACK received
ACK/NAK sent
Rx buffer full
Tx buffer empty
Stop generated
Start generated
D1
IMEIF
Overrun error flag
1 Error
0 Normal
0
R/W Reset by writing 1.
D0
IMIF
Operation completion flag
1 Completed 0 Not completed
0
R/W
USI Ch.0 I2C
Slave Mode
Trigger Register
(USI_ISTG0)
0x50cd
(8 bits)
D7–5 –
reserved
–
0 when being read.
D4
ISTG
I2C slave operation trigger
1 Trigger
0 Ignored
0
W
1 Waiting
0 Finished
R
D3
–
reserved
–
0 when being read.
D2–0 ISTGMOD
[2:0]
I2C slave trigger mode select
ISTGMOD[2:0] Trigger mode
0x0 R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
Receive ACK/NAK
Transmit NAK
Transmit ACK
Receive data
Transmit data
reserved
Wait for start