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3 MEMORY MAP, BUS CONTROL
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
3-1
Memory Map, Bus Control
3
Figure 3.1 shows the S1C17554/564 memory map.
Flash area
(128K bytes)
(Device size: 16 bits)
Vector table
Internal peripheral area 2
(4K bytes)
Internal peripheral area 1
(1K bytes)
Reserved for core I/O area
(1K bytes)
reserved
0xff ffff
0xff fc00
0xff fbff
0x02 8000
0x02 7fff
0x00 8000
0x00 7fff
0x00 6000
0x00 5fff
0x00 5000
0x00 4fff
0x00 4400
0x00 43ff
0x00 4000
0x00 3fff
0x00 3fc0
0x00 0000
0x43c0–0x43ff
0x4380–0x43bf
0x4360–0x437f
0x4340–0x435f
0x4320–0x433f
0x42e0–0x431f
0x4280–0x42df
0x4220–0x427f
0x4200–0x421f
0x4140–0x41ff
0x4100–0x413f
0x4040–0x40ff
0x4020–0x403f
0x4000–0x401f
reserved
SPI Ch.1–2
I2C slave
I2C master
SPI Ch.0
Interrupt controller
Fine mode 16-bit timer Ch.1
16-bit timer Ch.0–2
Fine mode 16-bit timer Ch.0
reserved
UART Ch.0–1
reserved
MISC registers
reserved
Debug RAM area (64 bytes)
Internal RAM area
(16K bytes)
(Device size: 32 bits)
0x5500–0x5fff
0x5480–0x54ff
0x5400–0x547f
0x53a0–0x53ff
0x5380–0x539f
0x5360–0x537f
0x5340–0x535f
0x5320–0x533f
0x52c0–0x531f
0x52a0–0x52bf
0x5280–0x529f
0x5200–0x527f
0x5140–0x51ff
0x5120–0x513f
0x5100–0x511f
0x50c0–0x50ff
0x50a0–0x50bf
0x5060–0x509f
0x5040–0x505f
0x5020–0x503f
0x5000–0x501f
reserved
Flash controller
16-bit PWM timer Ch.0–3
reserved
A/D converter
reserved
IR remote controller
MISC registers
reserved
Port MUX
reserved
P ports
reserved
Power generator (S1C17564)
reserved
USI Ch.0–1 (S1C17564)
reserved
Clock generator
Watchdog timer
Stopwatch timer
Clock timer
–
(16 bits)
–
(16 bits)
–
(16 bits)
–
(8 bits)
–
(8 bits)
–
(8 bits)
–
(8 bits)
–
(8 bits)
–
(16 bits)
–
(8 bits)
–
(8 bits)
–
Peripheral function
(Device size)
1 S1C17554/564 Memory Map
Figure 3.
Bus Cycle
3.1
The CPU uses the system clock for bus access operations. For more information on the system clock, see “System
Clock Switching” in the “Clock Generator (CLG)” chapter.
Note that the Flash area and other areas require different number of system clocks for one bus cycle as follows:
Instruction/data read from areas other than the Flash area:
One system clock per one bus cycle
Instruction read from the Flash area:
One to three system clocks or equivalent per one bus cycle
Data read from the Flash area:
Two to four system clocks per one bus cycle
Furthermore, the number of bus accesses depends on the CPU instruction (access size) and device size.