18 I2C SLAVE (I2CS)
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
18-5
If data has not been written in this period, the current register value (previous transmit data) will be sent.
In this case, TXUDF/I2CS_STAT register is set to 1 to indicate that invalid data has been sent. An interrupt
can be generated when TXUDF is set to 1, so an error handling should be performed in the interrupt han-
dler routine. TXUDF is cleared by writing 1.
When the clock stretch function is enabled
When the clock stretch function has been enabled, the I2CS module pulls down the SCL1 pin to low to gen-
erate a clock stretch (wait) status until transmit data is written to the I2CS_TRNS register.
Transmit data bits are output from the SDA1 pin in sync with the SCL1 input clock sent from the master. The
MSB is output first. After the eight bits has been output, the master sends back an ACK or NAK in the ninth
clock cycle.
SDA1 (output)
SDA1 (input)
SCL1 (input)
12
89
D7
D6
D0
ACK
NAK
5.2 ACK and NAK
Figure 18.
The ACK bit indicates that the master could receive data. It is also a transmit request bit, therefore, the next
transmit data must be written in advance. Receiving an ACK generates a clock stretch status when the clock
stretch function has been enabled, so data can be written after an ACK is received.
A NAK will be returned from the master if the master could not receive data or when the master terminates data
reception. In this case a clock stretch status is not generated even if the clock stretch function has been enabled.
Read DA_NAK/I2CS_STAT register to check if an ACK is returned or if a NAK is returned. DA_NAK is set to
0 when an ACK is returned or set to 1 when a NAK is returned. An interrupt can be generated when DA_NAK
is set to 1, so an error or termination handling can be performed in the interrupt handler routine. DA_NAK is
cleared by writing 1.
The SDA line status during data transmission is input in the module and is compare with the output data. The
comparison results are set to DMS/I2CS_STAT register. DMS is set to 0 when data is output correctly. If the
SDA line status is different from the output data, DMS is set to 1. This may be caused by a low pull-up resistor
value or another device that is controlling the SDA line. An interrupt can be generated when DMS is set to 1, so
an error handling can be performed in the interrupt handler routine. DMS is cleared by writing 1.
Note: If the I2CS module has sent back a NAK as the response to the address sent by the master when
the conditions shown below are all met, the master must wait for 33 s or more before it can send
another slave address (except when the master sends the I2CS slave address again).
1. More than one slave device is connected to the I2C bus.
2. The transfer rate is set to 320 kbps or higher.
3. The asynchronous address detection function is enabled.
4. The I2CS module is placed into transfer standby state and OSC1 is used as the operating
clock (PCLK).
Data reception
The following describes a data receive procedure.
The I2CS module starts data receiving process when SELECTED is set to 1 and R/W is set to 0. The received
data bits are input from the SDA1 pin in sync with the SCL1 input clock sent from the master. When the eight-
bit data (MSB first) is received in the shift register, the received data is loaded to RDATA[7:0]/I2CS_RECV
register.
When the received data is loaded to RDATA[7:0], RXRDY/I2CS_ASTAT register is set to 1 to issue a request
to the application program to read RDATA[7:0]. An interrupt can be generated when RXRDY is set to 1, so the
received data should be read in the interrupt handler routine. RXRDY is cleared by reading the received data.