19 UNIVERSAL SERIAL INTERFACE (USI) [S1C17564]
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
19-27
D0
UTDIF: Transmit Data Buffer Empty Flag Bit
Indicates the transmit data buffer status.
1 (R):
Empty (default)
0 (R):
Data exists
1 (W):
Reset to 0
0 (W):
Ignored
UTDIF is set to 1 when the transmit data written to the transmit data buffer is transferred to the shift
register (when transmission starts), indicating that the next transmit data can be written to. At the same
time a transmit buffer empty interrupt request is sent to the ITC if UTDIE/USI_UIEx register is 1.
UTDIF is reset by writing 1.
USI Ch.x SPI Master Mode Configuration Registers (USI_SCFGx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
USI Ch.x SPI
Master Mode
Configuration
Register
(USI_SCFGx)
0x50c6
0x50e6
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5
SCMD
Command bit (for 9-bit data)
1 High
0 Low
0
R/W
D4
SCHLN
Character length select
1 9 bits
0 8 bits
0
R/W
D3
SCPHA
Clock phase select
1 Phase 1
0 Phase 0
0
R/W
D2
SCPOL
Clock polarity select
1 Active L
0 Active H
0
R/W
D1
SMSKEN
Receive data mask enable
1 Enable
0 Disable
0
R/W
D0
SFSTMOD Fast mode select
1 Fast
0 Normal
0
R/W
Note: This register is effective only in SPI master mode. Configure the USI channel to SPI master mode
before this register can be used.
D[7:6]
Reserved
D5
SCMD: Command Bit (for 9-bit data)
Sets the command bit value for 9-bit data (see SCHLN below).
1 (R/W): High
0 (R/W): Low (default)
D4
SCHLN: Character Length Select Bit
Selects the serial transfer data length.
1 (R/W): 9 bits
0 (R/W): 8 bits (default)
In 9-bit mode, 8-bit data is prefixed with a command bit (1 bit). The command bit is used for control-
ling the SPI LCD controller connected to the USI. The command bit value to be transmitted can be
specified using SCMD.
SCHLN = 0, SCMD =
*
SCHLN = 1, SCMD = 0
SCHLN = 1, SCMD = 1
Command bit
D7 (D0) D6 (D1) D5 (D2) D4 (D3) D3 (D4) D2 (D5) D1 (D6) D0 (D7)
8.1 9-bit Transfer Data Format in SPI Master Mode
Figure 19.
D3
SCPHA: Clock Phase Select Bit
Selects the SPI clock phase.
1 (R/W): Phase 1
0 (R/W): Phase 0 (default)
Set the data transfer timing together with SCPOL. (See Figure 19.8.2.)
D2
SCPOL: Clock Polarity Select Bit
Selects the SPI clock polarity.
1 (R/W): Active low
0 (R/W): Active high (default)
Set the data transfer timing together with SCPHA. (See Figure 19.8.2.)