8 I/O PORTS (P)
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
8-5
Interrupt port selection
Select the port generating an interrupt using PxIEy/Px_IMSK register.
Setting PxIEy to 1 enables interrupt generation by the corresponding port. Setting to 0 (default) disables inter-
rupt generation.
Interrupt edge selection
Port input interrupts can be generated at either the rising edge or falling edge of the input signal. Select the edge
used to generate interrupts using PxEDGEy/Px_EDGE register.
Setting PxEDGEy to 1 generates port input interrupts at the input signal falling edge. Setting it to 0 (default)
generates interrupts at the rising edge.
Interrupt flags
The ITC is able to accept six interrupt requests from the P0–P5 ports, and the P port module contains interrupt
flags PxIFy/Px_IFLG register corresponding to the individual 40 ports to enable individual control of the 40
Pxy port interrupts. PxIFy is set to 1 at the specified edge (rising or falling edge) of the input signal. If the cor-
responding PxIEy has been set to 1, an interrupt request signal is also output to the ITC at the same time. An
interrupt is generated if the ITC and S1C17 Core interrupt conditions are satisfied.
PxIFy is reset by writing 1.
For specific information on interrupt processing, see the “Interrupt Controller (ITC)” chapter.
Notes: The P port module interrupt flag PxIFy must be reset in the interrupt handler routine after a
port interrupt has occurred to prevent recurring interrupts.
To prevent generating unnecessary interrupts, reset the relevant PxIFy before enabling inter-
rupts for the required port using PxIEy.
P0 Port Key-Entry Reset
8.7
Entering low level simultaneously to the ports (P00–P03) selected with software triggers an initial reset. The ports
used for the reset function can be selected with the P0KRST[1:0]/P0_KRST register.
7.1 Configuration of P0 Port Key-Entry Reset
Table 8.
P0KRST[1:0]
Port used for resetting
0x3
P00, P01, P02, P03
0x2
P00, P01, P02
0x1
P00, P01
0x0
Not used
(Default: 0x0)
For example, if P0KRST[1:0] is set to 0x3, an initial reset will take place when the four ports P00–P03 are set to
low level at the same time.
Note: The P0 port key-entry reset function cannot be used for power-on reset as it must be enabled with
software.
Control Register Details
8.8
8.1 List of I/O Port Control Registers
Table 8.
Address
Register name
Function
0x5200
P0_IN
P0 Port Input Data Register
P0 port input data
0x5201
P0_OUT
P0 Port Output Data Register
P0 port output data
0x5202
P0_OEN
P0 Port Output Enable Register
Enables P0 port outputs.
0x5203
P0_PU
P0 Port Pull-up Control Register
Controls the P0 port pull-up resistor.
0x5205
P0_IMSK
P0 Port Interrupt Mask Register
Enables P0 port interrupts.
0x5206
P0_EDGE
P0 Port Interrupt Edge Select Register
Selects the signal edge for generating P0 port interrupts.
0x5207
P0_IFLG
P0 Port Interrupt Flag Register
Indicates/resets the P0 port interrupt occurrence status.
0x5208
P0_CHAT
P0 Port Chattering Filter Control Register
Controls the P0 port chattering filter.
0x5209
P0_KRST
P0 Port Key-Entry Reset Configuration Register Configures the P0 port key-entry reset function.