APPENDIX A LIST OF I/O REGISTERS
AP-A-26
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
P5[5:4] Port
Function Select
Register
(P54_55PMUX)
0x52ab
(8 bits)
D7–4 –
reserved
–
0 when being read.
D3–2 P55MUX[1:0] P55 port function select
P55MUX[1:0]
Function
0x0 R/W
* S1C17564 only
0x3
0x2
0x1
0x0
reserved
US_SCK1*
P55
D1–0 P54MUX[1:0] P54 port function select
P54MUX[1:0]
Function
0x0 R/W
0x3
0x2
0x1
0x0
reserved
US_SDO1*
P54
0x4020, 0x5322–0x532c
MISC Registers
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Debug Mode
Control
Register 1
(MISC_DMODE1)
0x4020
(8 bits)
D7–2 –
reserved
–
0 when being read.
D1
DBRUN1
Run/stop select in debug mode
1 Run
0 Stop
0
R/W
D0
–
reserved
–
0 when being read.
Debug Mode
Control
Register 2
(MISC_DMODE2)
0x5322
(16 bits)
D15–1 –
reserved
–
0 when being read.
D0
DBRUN2
Run/stop select in debug mode
(except PCLK peripheral circuits)
1 Run
0 Stop
0
R/W
MISC Protect
Register
(MISC_PROT)
0x5324
(16 bits)
D15–0 PROT[15:0] MISC register write protect
Writing 0x96 removes the write
protection of the MISC regis-
ters (0x5326–0x532a).
Writing another value set the
write protection.
0x0 R/W
IRAM Size
Register
(MISC_IRAMSZ)
0x5326
(16 bits)
D15–9 –
reserved
–
0 when being read.
D8
DBADR
Debug base address select
1 0x0
0 0xfffc00
0
R/W
D7
–
reserved
–
0 when being read.
D6–4 IRAMACTSZ
[2:0]
IRAM actual size
0x6 (= 16KB)
0x6
R
D3
–
reserved
–
0 when being read.
D2–0 IRAMSZ[2:0] IRAM size select
IRAMSZ[2:0]
Size
0x6 R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
16KB
512B
1KB
2KB
4KB
8KB
12KB
Vector Table
Address Low
Register
(MISC_TTBRL)
0x5328
(16 bits)
D15–8 TTBR[15:8] Vector table base address A[15:8]
0x0–0xff
0x80 R/W
D7–0 TTBR[7:0]
Vector table base address A[7:0]
(fixed at 0)
0x0
R
Vector Table
Address High
Register
(MISC_TTBRH)
0x532a
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7–0 TTBR[23:16] Vector table base address
A[23:16]
0x0–0xff
0x0 R/W
PSR Register
(MISC_PSR)
0x532c
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7–5 PSRIL[2:0] PSR interrupt level (IL) bits
0x0 to 0x7
0x0
R
D4
PSRIE
PSR interrupt enable (IE) bit
1 1 (enable)
0 0 (disable)
0
R
D3
PSRC
PSR carry (C) flag
1 1 (set)
0 0 (cleared)
0
R
D2
PSRV
PSR overflow (V) flag
1 1 (set)
0 0 (cleared)
0
R
D1
PSRZ
PSR zero (Z) flag
1 1 (set)
0 0 (cleared)
0
R
D0
PSRN
PSR negative (N) flag
1 1 (set)
0 0 (cleared)
0
R