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APPENDIX A LIST OF I/O REGISTERS
AP-A-2
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
Peripheral
Address
Register name
Function
SPI Ch.0
(16-bit device)
0x4320
SPI_ST0
SPI Ch.0 Status Register
Indicates transfer and buffer statuses.
0x4322
SPI_TXD0
SPI Ch.0 Transmit Data Register
Transmit data
0x4324
SPI_RXD0
SPI Ch.0 Receive Data Register
Receive data
0x4326
SPI_CTL0
SPI Ch.0 Control Register
Sets the SPI mode and enables data transfer.
I2C master
(16-bit device)
0x4340
I2CM_EN
I2C Master Enable Register
Enables the I2C master module.
0x4342
I2CM_CTL
I2C Master Control Register
Controls the I2C master operation and
indicates transfer status.
0x4344
I2CM_DAT
I2C Master Data Register
Transmit/receive data
0x4346
I2CM_ICTL
I2C Master Interrupt Control Register
Controls the I2C master interrupt.
I2C slave
(16-bit device)
0x4360
I2CS_TRNS
I2C Slave Transmit Data Register
I2C slave transmit data
0x4362
I2CS_RECV
I2C Slave Receive Data Register
I2C slave receive data
0x4364
I2CS_SADRS
I2C Slave Address Setup Register
Sets the I2C slave address.
0x4366
I2CS_CTL
I2C Slave Control Register
Controls the I2C slave module.
0x4368
I2CS_STAT
I2C Slave Status Register
Indicates the I2C bus status.
0x436a
I2CS_ASTAT
I2C Slave Access Status Register
Indicates the I2C slave access status.
0x436c
I2CS_ICTL
I2C Slave Interrupt Control Register
Controls the I2C slave interrupt.
SPI Ch.1
(16-bit device)
0x4380
SPI_ST1
SPI Ch.1 Status Register
Indicates transfer and buffer statuses.
0x4382
SPI_TXD1
SPI Ch.1 Transmit Data Register
Transmit data
0x4384
SPI_RXD1
SPI Ch.1 Receive Data Register
Receive data
0x4386
SPI_CTL1
SPI Ch.1 Control Register
Sets the SPI mode and enables data transfer.
SPI Ch.2
(16-bit device)
0x43a0
SPI_ST2
SPI Ch.2 Status Register
Indicates transfer and buffer statuses.
0x43a2
SPI_TXD2
SPI Ch.2 Transmit Data Register
Transmit data
0x43a4
SPI_RXD2
SPI Ch.2 Receive Data Register
Receive data
0x43a6
SPI_CTL2
SPI Ch.2 Control Register
Sets the SPI mode and enables data transfer.
Internal Peripheral Circuit Area 2 (0x5000–0x5fff)
Peripheral
Address
Register name
Function
Clock timer
(8-bit device)
0x5000
CT_CTL
Clock Timer Control Register
Resets and starts/stops the timer.
0x5001
CT_CNT
Clock Timer Counter Register
Counter data
0x5002
CT_IMSK
Clock Timer Interrupt Mask Register
Enables/disables interrupt.
0x5003
CT_IFLG
Clock Timer Interrupt Flag Register
Indicates/resets interrupt occurrence status.
Stopwatch
timer
(8-bit device)
0x5020
SWT_CTL
Stopwatch Timer Control Register
Resets and starts/stops the timer.
0x5021
SWT_BCNT
Stopwatch Timer BCD Counter Register
BCD counter data
0x5022
SWT_IMSK
Stopwatch Timer Interrupt Mask Register
Enables/disables interrupt.
0x5023
SWT_IFLG
Stopwatch Timer Interrupt Flag Register
Indicates/resets interrupt occurrence status.
Watchdog timer
(8-bit device)
0x5040
WDT_CTL
Watchdog Timer Control Register
Resets and starts/stops the timer.
0x5041
WDT_ST
Watchdog Timer Status Register
Sets the timer mode and indicates NMI status.
Clock generator
(8-bit device)
(T16A, UART)
0x5060
CLG_SRC
Clock Source Select Register
Selects the clock source.
0x5061
CLG_CTL
Oscillation Control Register
Controls oscillation.
0x5062
CLG_NFEN
Noise Filter Enable Register
Turns oscillation stabilization wait circuit/
noise filter on/off.
0x5064
CLG_FOUTA
FOUTA Control Register
Controls FOUTA clock output.
0x5065
CLG_FOUTB
FOUTB Control Register
Controls FOUTB clock output.
0x5068
T16A_CLK0
T16A Clock Control Register Ch.0
Controls the T16A Ch.0 clock.
0x5069
T16A_CLK1
T16A Clock Control Register Ch.1
Controls the T16A Ch.1 clock.
0x506a
T16A_CLK2
T16A Clock Control Register Ch.2
Controls the T16A Ch.2 clock.
0x506b
T16A_CLK3
T16A Clock Control Register Ch.3
Controls the T16A Ch.3 clock.
0x506c
UART_CLK0
UART Ch.0 Clock Control Register
Selects the baud rate generator clock.
0x506d
UART_CLK1
UART Ch.1 Clock Control Register
Selects the baud rate generator clock.
0x506e
CLG_IOSC
IOSC Control Register
Configures IOSC oscillation frequency.
0x5080
CLG_PCLK
PCLK Control Register
Controls the PCLK supply.
0x5081
CLG_CCLK
CCLK Control Register
Configures the CCLK division ratio.
USI Ch.0
(8-bit device)
0x50c0
USI_GCFG0
USI Ch.0 Global Configuration Register
Sets interface and MSB/LSB mode.
0x50c1
USI_TD0
USI Ch.0 Transmit Data Buffer Register
Transmit data buffer
0x50c2
USI_RD0
USI Ch.0 Receive Data Buffer Register
Receive data buffer
0x50c3
USI_UCFG0
USI Ch.0 UART Mode Configuration Register
Sets UART transfer conditions.
0x50c4
USI_UIE0
USI Ch.0 UART Mode Interrupt Enable Register Enables interrupts.
0x50c5
USI_UIF0
USI Ch.0 UART Mode Interrupt Flag Register
Indicates interrupt occurrence status.
0x50c6
USI_SCFG0
USI Ch.0 SPI Master Mode Configuration
Register
Sets SPI transfer conditions.
0x50c7
USI_SIE0
USI Ch.0 SPI Master Mode Interrupt Enable
Register
Enables interrupts.
0x50c8
USI_SIF0
USI Ch.0 SPI Master Mode Interrupt Flag
Register
Indicates interrupt occurrence status.
0x50c9
USI_SMSK0
USI Ch.0 SPI Master Mode Receive Data Mask
Register
Sets receive data mask.
0x50ca
USI_IMTG0
USI Ch.0 I2C Master Mode Trigger Register
Starts I2C master operations.