13 STOPWATCH TIMER (SWT)
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
13-5
Note: The correct counter value may not be read out (reading is unstable) if the register is read while
counting is underway. Read the counter register twice in succession and treat the value as valid if
the values read are identical.
Stopwatch Timer Interrupt Mask Register (SWT_IMSK)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Stopwatch
Timer Interrupt
Mask Register
(SWT_IMSK)
0x5022
(8 bits)
D7–3 –
reserved
–
0 when being read.
D2
SIE1
1 Hz interrupt enable
1 Enable
0 Disable
0
R/W
D1
SIE10
10 Hz interrupt enable
1 Enable
0 Disable
0
R/W
D0
SIE100
100 Hz interrupt enable
1 Enable
0 Disable
0
R/W
This register enables or disables interrupt requests individually for the 100 Hz, 10 Hz, and 1 Hz signals. Setting
SIE* to 1 enables SWT interrupts for the corresponding frequency signal falling edge, while setting to 0 disables
interrupts.
D[7:3]
Reserved
D2
SIE1: 1 Hz Interrupt Enable Bit
Enables or disables 1 Hz interrupts.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
D1
SIE10: 10 Hz Interrupt Enable Bit
Enables or disables 10 Hz interrupts.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
D0
SIE100: 100 Hz Interrupt Enable Bit
Enables or disables 100 Hz interrupts.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
Stopwatch Timer Interrupt Flag Register (SWT_IFLG)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Stopwatch
Timer Interrupt
Flag Register
(SWT_IFLG)
0x5023
(8 bits)
D7–3 –
reserved
–
0 when being read.
D2
SIF1
1 Hz interrupt flag
1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.
D1
SIF10
10 Hz interrupt flag
0
R/W
D0
SIF100
100 Hz interrupt flag
0
R/W
This register indicates the occurrence state of interrupt causes due to 100 Hz, 10 Hz, and 1 Hz signals. If an SWT
interrupt occurs, identify the interrupt cause (frequency) by reading the interrupt flag in this register. SIF* is an
SWT module interrupt flag that is set to 1 at the falling edge of the corresponding 100 Hz, 10 Hz, or 1 Hz interrupt.
SIF* is reset by writing 1.
D[7:3]
Reserved
D2
SIF1: 1 Hz Interrupt Flag Bit
Indicates whether the cause of 1 Hz interrupt has occurred or not.
1 (R):
Cause of interrupt has occurred
0 (R):
No cause of interrupt has occurred (default)
1 (W):
Flag is reset
0 (W):
Ignored
D1
SIF10: 10 Hz Interrupt Flag Bit
Indicates whether the cause of 10 Hz interrupt has occurred or not.
1 (R):
Cause of interrupt has occurred
0 (R):
No cause of interrupt has occurred (default)
1 (W):
Flag is reset
0 (W):
Ignored