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7 CLOCK GENERATOR (CLG)
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
7-5
OSC1 oscillation on/off
The OSC1 oscillator stops oscillating when OSC1EN/CLG_CTL register is set to 0 and starts oscillating when
set to 1. The OSC1 oscillator circuit stops oscillating in SLEEP mode.
After an initial reset, OSC1EN is set to 0, and the OSC1 oscillator circuit is halted.
Stabilization wait time at start of OSC1 oscillation
The OSC1 oscillator includes an oscillation stabilization wait circuit (fixed at 256 cycles) to prevent malfunc-
tions caused by unstable clock operations at the start of OSC1 oscillation—e.g., when the OSC1 oscillator is
turned on with software. When the system clock is switched to OSC1 immediately after the OSC1 oscillator
circuit is turned on, the OSC1 clock is supplied to the system after the OSC1 clock system supply wait time
indicated below (at a maximum) has elapsed. For the oscillation start time, see the “Electrical Characteristics”
chapter.
OSC1 clock system supply wait time
≤ OSC1 oscillation start time (max.) + OSC1 oscillation stabilization
wait time (256 cycles)
The OSC1 oscillation stabilization wait circuit can be enabled or disabled using OSC1WCE/CLG_NFEN
register. After an initial reset, the OSC1 oscillation stabilization wait circuit is enabled (OSC1WCE = 1) and
it controls the clock supply to the system. When a stabilized external clock is input to the OSC1 pin, setting
OSC1WCE to 0 enables the system to start operating without a stabilization wait time.
IOSC Oscillator (S1C17564)
7.3.3
The IOSC oscillator initiates high-speed oscillation without external components. It initiates oscillation when pow-
er is turned on. The S1C17 Core and peripheral circuits operates with this oscillation clock after an initial reset.
fIOSC
Clock
generator
IOSCEN
Oscillation stabilization
wait circuit
IOSCWT[1:0]
3.3.1 IOSC Oscillator Circuit
Figure 7.
IOSC oscillation frequency
The IOSC oscillation frequency can be selected from four types shown below using IOSCSEL[1:0]/CLG_IOSC
register.
3.3.1 IOSC Oscillation Frequency Setting
Table 7.
IOSCSEL[1:0]
IOSC oscillation frequency (typ.)
0x3
2 MHz
0x2
4 MHz
0x1
12 MHz
0x0
8 MHz
(Default: 0x1)
IOSC oscillation on/off
The IOSC oscillator stops oscillating when IOSCEN/CLG_CTL register is set to 0 and starts oscillating when
set to 1. The IOSC oscillator stops oscillating in SLEEP mode.
After an initial reset, IOSCEN is set to 1, and the IOSC oscillator goes on. Since the IOSC clock is used as the
system clock, the S1C17 Core starts operating using the IOSC clock.
When SLEEP mode is canceled, the IOSC oscillator circuit is turned on and is used as the system clock source
regardless of the system clock configured before the chip entered SLEEP mode.
Stabilization wait time at start of IOSC oscillation
The IOSC oscillator circuit includes an oscillation stabilization wait circuit to prevent malfunctions due to
unstable clock operations at the start of IOSC oscillation—e.g., when the IOSC oscillator is turned on with
software. The IOSC clock is not supplied to the system until the time set for this circuit has elapsed. Use
IOSCWT[1:0]/CLG_CTL register to select one of four oscillation stabilization wait times.