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19 UNIVERSAL SERIAL INTERFACE (USI) [S1C17564]
19-30
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
USI Ch.x SPI Master Mode Receive Data Mask Registers (USI_SMSKx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
USI Ch.x SPI
Master Mode
Receive Data
Mask Register
(USI_SMSKx)
0x50c9
0x50e9
(8 bits)
D7–0 SMSK[7:0] Receive data mask bit
SMSK7 = MSB
SMSK0 = LSB
0x0 to 0xff
0x0 R/W
Note: This register is effective only in SPI master mode. Configure the USI channel to SPI master mode
before this register can be used.
D[7:0]
SMSK[7:0]: Receive Data Mask Bits
Sets the mask data for the receive data mask function. (Default: 0x0)
The USI in SPI master mode provides a receive data mask (data retransmission) function. Setting SM-
SKEN/USI_SCFGx to 1 enables this function. When the receive data mask function is enabled, the USI
transmits the data stored in the transmit data buffer repeatedly until the slave device sends back a value
other than the mask data set to SMSK[7:0]. In this case, the transmit buffer empty and receive data buf-
fer full interrupt flags are not set and no interrupt is generated. In other words, the USI does not accept
the receive data while the slave device is transmitting the mask data.
USI Ch.x I2C Master Mode Trigger Registers (USI_IMTGx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
USI Ch.x I2C
Master Mode
Trigger Register
(USI_IMTGx)
0x50ca
0x50ea
(8 bits)
D7–5 –
reserved
–
0 when being read.
D4
IMTG
I2C master operation trigger
1 Trigger
0 Ignored
0
W
1 Waiting
0 Finished
R
D3
–
reserved
–
0 when being read.
D2–0 IMTGMOD
[2:0]
I2C master trigger mode select
IMTGMOD[2:0] Trigger mode
0x0 R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
Receive ACK/NAK
Transmit NAK
Transmit ACK
Receive data
Transmit data
Stop condition
Start condition
Note: This register is effective only in I2C master mode. Configure the USI channel to I2C master mode
before this register can be used.
D[7:5]
Reserved
D4
IMTG: I2C Master Operation Trigger Bit
Starts an I2C master operation.
1 (W):
Trigger
0 (W):
Ignored
1 (R):
Waiting for starting operation
0 (R):
Trigger has finished (default)
Select an I2C master operation using IMTGMOD[2:0] and write 1 to IMTG as the trigger. The I2C con-
troller controls the I2C bus to generate the specified operating status.
D3
Reserved
D[2:0]
IMTGMOD[2:0]: I2C Master Trigger Mode Select Bits
Selects an I2C master operation.
8.3 Trigger List in I
Table 19.
2C Master Mode
IMTGMOD[2:0]
Trigger
0x7
Reserved
0x6
ACK/NAK reception
0x5
NAK transmission
0x4
ACK transmission
0x3
Data reception
0x2
Data transmission
0x1
Stop condition
0x0
Start condition
(Default: 0x0)