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19 UNIVERSAL SERIAL INTERFACE (USI) [S1C17564]
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
19-25
D0
UPREN: Parity Enable Bit
Enables the parity function.
1 (R/W): With parity
0 (R/W): No parity (default)
UPREN is used to select whether received data parity checking is performed and whether a parity bit
is added to transmit data. Setting UPREN to 1 parity-checks the received data. A parity bit is automati-
cally added to the transmit data. If UPREN is set to 0, no parity bit is checked or added.
USI Ch.x UART Mode Interrupt Enable Registers (USI_UIEx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
USI Ch.x UART
Mode Interrupt
Enable Register
(USI_UIEx)
0x50c4
0x50e4
(8 bits)
D7–3 –
reserved
–
0 when being read.
D2
UEIE
Receive error interrupt enable
1 Enable
0 Disable
0
R/W
D1
URDIE
Receive buffer full interrupt enable 1 Enable
0 Disable
0
R/W
D0
UTDIE
Transmit buffer empty int. enable
1 Enable
0 Disable
0
R/W
Note: This register is effective only in UART mode. Configure the USI channel to UART mode before
this register can be used.
D[7:3]
Reserved
D2
UEIE: Receive Error Interrupt Enable Bit
Enables interrupt requests to the ITC when a receive error occurs.
1 (R/W): Enabled
0 (R/W): Disabled (default)
Set this bit to 1 to process receive errors using interrupts.
D1
URDIE: Receive Buffer Full Interrupt Enable Bit
Enables interrupt requests to the ITC when received data is loaded to the receive data buffer.
1 (R/W): Enabled
0 (R/W): Disabled (default)
Set this bit to 1 to read received data using interrupts.
D0
UTDIE: Transmit Buffer Empty Interrupt Enable Bit
Enables interrupt requests to the ITC when data written to the transmit data buffer is sent to the shift
register (i.e. when data transmission begins).
1 (R/W): Enabled
0 (R/W): Disabled (default)
Set this bit to 1 to write data to the transmit data buffer using interrupts.
USI Ch.x UART Mode Interrupt Flag Registers (USI_UIFx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
USI Ch.x UART
Mode Interrupt
Flag Register
(USI_UIFx)
0x50c5
0x50e5
(8 bits)
D7
–
reserved
–
0 when being read.
D6
URBSY
Receive busy flag
1 Busy
0 Idle
0
R
D5
UTBSY
Transmit busy flag
1 Busy
0 Idle
0
R
D4
UPEIF
Parity error flag
1 Error
0 Normal
0
R/W Reset by writing 1.
D3
USEIF
Framing error flag
1 Error
0 Normal
0
R/W
D2
UOEIF
Overrun error flag
1 Error
0 Normal
0
R/W
D1
URDIF
Receive buffer full flag
1 Full
0 Not full
0
R/W
D0
UTDIF
Transmit buffer empty flag
1 Empty
0 Not empty
0
R/W
Note: This register is effective only in UART mode. Configure the USI channel to UART mode before
this register can be used.
D7
Reserved
D6
URBSY: Receive Busy Flag Bit
Indicates the receive shift register status.
1 (R):
Busy
0 (R):
Idle (default)