![](http://datasheet.mmic.net.cn/120000/S1C17564F00E10C_datasheet_3574343/S1C17564F00E10C_211.png)
19 UNIVERSAL SERIAL INTERFACE (USI) [S1C17564]
19-24
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
In UART and SPI master mode, transmission begins immediately after writing data to this register.
In I2C master/slave mode, transmission begins by the software trigger for data transmission.
The data written to this register is converted into serial data through the shift register and is output from
the US_SDOx pin with the bit set to 1 as high level and the bit set to 0 as low level.
A transmit buffer empty interrupt can be generated when data written to this register has been trans-
ferred to the shift register. The subsequent transmit data can then be written, even while data is being
sent.
USI Ch.x Receive Data Buffer Registers (USI_RDx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
USI Ch.x
Receive Data
Buffer Register
(USI_RDx)
0x50c2
0x50e2
(8 bits)
D7–0 RD[7:0]
USI receive data buffer
RD7 = MSB
RD0 = LSB
0x0 to 0xff
0x0
R
D[7:0]
RD[7:0]: USI Receive Data Buffer Bits
Contains the received data. (Default: 0x0)
Serial data input from the US_SDIx pin is converted to parallel, with the high level bit set to 1 and the
low level bit set to 0, and then it is loaded to this register.
A receive buffer full interrupt can be generated when the data received in the shift register has been
loaded to this register. Data can then be read until subsequent data is received. If receiving the subse-
quent data is completed before the register has been read out, the new received data overwrites the con-
tents.
This register is read-only.
USI Ch.x UART Mode Configuration Registers (USI_UCFGx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
USI Ch.x
UART Mode
Configuration
Register
(USI_UCFGx)
0x50c3
0x50e3
(8 bits)
D7–4 –
reserved
–
0 when being read.
D3
UCHLN
Character length select
1 8 bits
0 7 bits
0
R/W
D2
USTPB
Stop bit select
1 2 bits
0 1 bit
0
R/W
D1
UPMD
Parity mode select
1 Even
0 Odd
0
R/W
D0
UPREN
Parity enable
1 With parity
0 No parity
0
R/W
Note: This register is effective only in UART mode. Configure the USI channel to UART mode before
setting this register.
D[7:4]
Reserved
D3
UCHLN: Character Length Select Bit
Selects the serial transfer data length.
1 (R/W): 8 bits
0 (R/W): 7 bits (default)
When 7-bit data length is selected, D7 in the transmit data buffer is ignored and D7 in the receive data
buffer is always set to 0.
D2
USTPB: Stop Bit Select Bit
Selects the stop bit length.
1 (R/W): 2 bits
0 (R/W): 1 bit (default)
Writing 1 to USTPB selects 2 stop bits; writing 0 to it selects 1 bit. The start bit is fixed at 1 bit.
D1
UPMD: Parity Mode Select Bit
Selects the parity mode.
1 (R/W): Even parity
0 (R/W): Odd parity (default)
Parity checking and parity bit addition are enabled only when UPREN is set to 1. The UPMD setting is
disabled if UPREN is 0.