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19 UNIVERSAL SERIAL INTERFACE (USI) [S1C17564]
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
19-31
USI Ch.x I2C Master Mode Interrupt Enable Registers (USI_IMIEx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
USI Ch.x I2C
Master Mode
Interrupt Enable
Register
(USI_IMIEx)
0x50cb
0x50eb
(8 bits)
D7–2 –
reserved
–
0 when being read.
D1
IMEIE
Receive error interrupt enable
1 Enable
0 Disable
0
R/W
D0
IMIE
Operation completion int. enable
1 Enable
0 Disable
0
R/W
Note: This register is effective only in I2C master mode. Configure the USI channel to I2C master mode
before this register can be used.
D[7:2]
Reserved
D1
IMEIE: Receive Error Interrupt Enable Bit
Enables interrupt requests to the ITC when an overrun error occurs.
1 (R/W): Enabled
0 (R/W): Disabled (default)
Set this bit to 1 to process overrun errors using interrupts.
D0
IMIE: Operation Completion Interrupt Enable Bit
Enables interrupt requests to the ITC when the triggered operation has completed.
1 (R/W): Enabled
0 (R/W): Disabled (default)
Set this bit to 1 to confirm whether the triggered operation has completed or not using interrupts.
USI Ch.x I2C Master Mode Interrupt Flag Registers (USI_IMIFx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
USI Ch.x I2C
Master Mode
Interrupt Flag
Register
(USI_IMIFx)
0x50cc
0x50ec
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5
IMBSY
I2C master busy flag
1 Busy
0 Standby
0
R
D4–2 IMSTA[2:0] I2C master status
IMSTA[2:0]
Status
0x0
R
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
NAK received
ACK received
ACK/NAK sent
Rx buffer full
Tx buffer empty
Stop generated
Start generated
D1
IMEIF
Overrun error flag
1 Error
0 Normal
0
R/W Reset by writing 1.
D0
IMIF
Operation completion flag
1 Completed 0 Not completed
0
R/W
Note: This register is effective only in I2C master mode. Configure the USI channel to I2C master mode
before this register can be used.
D[7:6]
Reserved
D5
IMBSY: I2C Master Busy Flag Bit
Indicates the I2C master operation status.
1 (R):
Busy
0 (R):
Standby (default)
Writing 1 to IMTG/USI_IMTGx register (starting an I2C master operation) sets IMBSY to 1 indicating
that the I2C controller is busy (operating). When the specified operation has finished, IMBSY is reset to 0.
D[4:2]
IMSTA[2:0]: I2C Master Status Bits
Indicates the I2C master status.