83
Table 2.25
System Control Instructions (cont)
Instruction
Instruction Code
Operation
Cycles
T
Bit
STS
MACH,Rn
0000nnnn00001010
MACH
→ Rn
1
—
STS
MACL,Rn
0000nnnn00011010
MACL
→ Rn
1
—
STS
PR,Rn
0000nnnn00101010
PR
→ Rn
1
—
STS
DSR,Rn
0000nnnn01101010
DSR
→ Rn
1
—
STS
A0,Rn
0000nnnn01111010
A0
→ Rn
1
—
STS
X0,Rn
0000nnnn10001010
X0
→ Rn
1
—
STS
X1,Rn
0000nnnn10011010
X1
→ Rn
1
—
STS
Y0,Rn
0000nnnn10101010
Y0
→ Rn
1
—
STS
Y1,Rn
0000nnnn10111010
Y1
→ Rn
1
—
STS.L
MACH,@–Rn
0100nnnn00000010
Rn – 4
→ Rn, MACH → (Rn) 1
—
STS.L
MACL,@–Rn
0100nnnn00010010
Rn – 4
→ Rn, MACL → (Rn)
1
—
STS.L
PR,@–Rn
0100nnnn00100010
Rn – 4
→ Rn, PR → (Rn)
1
—
STS.L
DSR,@–Rn
0100nnnn01100010
Rn – 4
→ Rn, DSR → (Rn)
1
—
STS.L
A0,@–Rn
0100nnnn01110010
Rn – 4
→ Rn, A0 → (Rn)
1
—
STS.L
X0,@–Rn
0100nnnn10000010
Rn – 4
→ Rn, X0 → (Rn)
1
—
STS.L
X1,@–Rn
0100nnnn10010010
Rn – 4
→ Rn, X1 → (Rn)
1
—
STS.L
Y0,@–Rn
0100nnnn10100010
Rn – 4
→ Rn, Y0 → (Rn)
1
—
STS.L
Y1,@–Rn
0100nnnn10110010
Rn – 4
→ Rn, Y1 → (Rn)
1
—
TRAPA
#imm
11000011iiiiiiii
PC/SR
→ stack area, (imm ×
4 + VBR)
→ PC
8—
Note:
The number of execution cycles (3) before the chip enters sleep mode.
Precautions Concerning the Number of Instruction Execution Cycles: The execution cycles
listed in the tables are minimum values. In practice, the number of execution cycles increases
under such conditions as follows:
When the instruction fetch is in contention with a data access
When the destination register of a load instruction (memory → register) is the same as the
register used by the next instruction
When the branch destination address of a branch instruction is a 4n + 2 address.
CPU Instructions That Support DSP Functions: A number of system control instructions have
been added to the CPU core instructions to support DSP functions. The RS, RE and MOD
registers have been added to support repeat control and modulo addressing, and the RC counter
has been added to the SR register. The LDC and STC instructions have been added in order to