xii
Figure 5.9
Interrupt Response Timing ..................................................................................... 161
Figure 6.1
User Break Controller Block Diagram ................................................................... 164
Figure 6.2
Case of Interrupt Occurring before Branch Destination Instruction Execution...... 183
Figure 7.1
BSC Block Diagram ............................................................................................... 195
Figure 7.2
32-Bit External Devices and Their Access Sizes.................................................... 210
Figure 7.3
16-Bit External Devices and Their Access Sizes.................................................... 210
Figure 7.4
8-Bit External Devices and Their Access Sizes...................................................... 211
Figure 7.5
32-Bit Data Width SRAM Connection Example.................................................... 213
Figure 7.6
16-Bit Data Width SRAM Connection Example.................................................... 214
Figure 7.7
8-Bit Data Width SRAM Connection Example...................................................... 214
Figure 7.8
Basic Timing of an Ordinary Space Access ........................................................... 215
Figure 7.9
Wait Timing of Ordinary Space Access (Software Wait Only) ............................. 216
Figure 7.10 Wait State Timing of Ordinary Space Access (Wait State from Software Wait 1
State + WAIT Signal) ............................................................................................. 217
Figure 7.11 DMA Single-Address Access Timing of an Ordinary Space Access ..................... 218
Figure 7.12 DRAM Connection (32-Bit Data Width) Example ................................................ 220
Figure 7.13 DRAM Connection (16-Bit Data Width) Example ................................................ 221
Figure 7.14 DRAM Connection (8-Bit Data Width) Example .................................................. 221
Figure 7.15 Basic DRAM Access Timing.................................................................................. 223
Figure 7.16 Basic EDO DRAM Access Timing ........................................................................ 224
Figure 7.17 DRAM Access Timing with Waits ......................................................................... 226
Figure 7.18 EDO DRAM Access Timing with Waits................................................................ 227
Figure 7.19 DRAM Burst-Access Timing ................................................................................. 229
Figure 7.20 EDO DRAM Burst-Access Timing ........................................................................ 230
Figure 7.21 RAS-Down Mode: Fast-Page Mode DRAM Read Timing (Same Row Access) .. 232
Figure 7.22 RAS-Down Mode: Fast-Page Mode DRAM Write Timing (Same Row Access).. 233
Figure 7.23 RAS-Down Mode: Fast-Page Mode DRAM Timing (Different Row Access) ...... 234
Figure 7.24 RAS-Down Mode: EDO DRAM Read Timing (Same Row Access) .................... 235
Figure 7.25 RAS-Down Mode: EDO DRAM Write Timing (Same Row Access).................... 236
Figure 7.26 RAS-Down Mode: EDO DRAM Timing (Different Row Access)........................ 237
Figure 7.27 DMA Single-Address Transfer Timing (Read with Wait) ..................................... 239
Figure 7.28 DMA Single-Address Transfer Timing (Write with Wait) .................................... 240
Figure 7.29 RAS-Down Mode: DMA Single-Address Transfer Timing (Same Row Access,
Read, No Wait) ....................................................................................................... 241
Figure 7.30 RAS-Down Mode: DMA Single-Address Transfer Timing (Same Row Access,
No Wait).................................................................................................................. 242
Figure 7.31 RAS-Down Mode: DMA Single-Address Transfer Timing (Same Row Access,
Read, with Wait) ..................................................................................................... 243
Figure 7.32 RAS-Down Mode: DMA Single-Address Transfer Timing (Same Row Access,
Write, With Wait) ................................................................................................... 244
Figure 7.33 DMA Single-Address Transfer Timing for EDO DRAM (Read, No Wait)........... 245
Figure 7.34 DMA Single-Address Transfer Timing for EDO DRAM (Write, No Wait).......... 246
Figure 7.35 DMA Single-Address Transfer Timing for EDO DRAM (Read with Wait).......... 247