206
Bit 4—Refresh Control (RFSH): Determines whether or not the refresh operation of the DRAM or
pseudo-SRAM is performed.
Bit 4: RFSH
Description
0
No refresh (initial value)
1
Refresh
Bit 3—Refresh Mode (RMODE): When the RFSH bit is set to 1, selects normal refresh or self-
refresh. When the RFSH bit is cleared to 0, do not set this bit to 1. When the RFSH bit is 1, self-
refresh mode is entered immediately after the RMODE bit is set to 1. When the RFSH bit is set
and this RMODE is cleared, a CAS-before-RAS refresh or auto-refresh is performed at the
interval set in the 8-bit interval timer (RTCNT). When a refresh request occurs during an external
area access, the access is allowed to finish before the refresh is performed. Refresh requests from
the interval timer are ignored during a self-refresh.
Bit 3: RMODE
Description
0
CAS-before-RAS refresh for DRAM or auto-refresh for pseudo-SRAM
(initial value)
1
Self-refresh
Bit 2—Burst Enable (BE): When memory area 2 or 3 is DRAM, this bit enables the burst transfer
in either fast-page mode or EDO mode. When memory area 3 is pseudo-SRAM, this bit enables
static column mode.
Bit 2: BE
Description
0
Burst disabled (initial value)
1
Burst transfer of fast-page mode or EDO mode during DRAM interface
is enabled. Data is continuously transferred in static column mode
during pseudo-SRAM interface.
Note:
Burst transfers are performed for the following types of DRAM/pseudo-SRAM accesses: 1)
word/longword accesses when bus width is 8-bit; 2) longword accesses when bus width is
16-bit.
Bit 1—RAS-Down Mode (RASD): When memory area 2 or 3 is DRAM and BE is set to 1, this bit
causes the processor to hold
RAS asserted after each access. When DRAM is not set by the
DRAM1 and DRAM0 bits in BCR1, this bit should be left as a 0.
Bit 1: RASD
Description
0
For DRAM, negates RAS assertion after each access (initial value).
1
For DRAM, RAS remains asserted after each access; negates RAS to
pre-charge before an access to a different page occurs.